Implementation Of Space Vector Pulse Width Modulation Research Articles

Minimum device usages of field programmable gate array (FPGA) verification of multilevel PWM inverter drive generation

Space Vector Pulse-Width Modulation (SVPWM) has now become an unavoidable PWM in the power electronics inverter development. If the SVPWM implementation can be made user-friendly, the operation can be easily soaked in by the future researchers and also the closed loop operation becomes sophisticated. This paper conveys a broad view about the state of art of different Field programmable gate array (FPGA) processors along with the inner views about the implementations of the 3-level SVPWM. The description of the different processors is discussed along with the implementation variance and also attempts to implement the SVPWM through Xilinx Spartan-III 3AN-XC3S400 using MATLAB-Xilinx System Generator (XSG) without deploying the direct Very High Speed Language (VHDL) code. It provides shortest translation designs into hardware implementations that are faithful, synthesizable and efficient, which permits the designer to minimise the time spent for the description and implementation of circuit. The synthesis result shows that the proposed implementation at 50 MHz frequency operation consumes a power of 13mW and occupies 1112 look up tables (LUTs) and 424 File File (FFs). Thereby, the Total Resource Utilization reduced drastically to 36%, which is far better than the other existing implementations. Also, the inference of less processing time can be seen from the synthesis.

Modified Space Vector Modulation Technique for Three Phase Three Level T-type Inverter

Today, multi-level inverters (MLIs) are widely used and applied in many fields, including renewable energy systems and industrial drive control, among others. Multi-level inverters are mainly modulated by Pulse Width Modulation (PWM) method, in which Space Vector Pulse Width Modulation (SVPWM) is a superior method. However, as the number of levels enhances, the implementation of SVPWM for multi-level inverters has many difficulties. In this paper, the two new pulse patterns corresponding to two switching sequences in space vector modulation are applied for the three-phase three-level T-type inverter. Experimental results will evidence the advantages of the proposed switching sequences. Furthermore, both switching sequences can be executed in real-time using a single Texas Instruments F28379D, demonstrating hardware simplicity.

Hybrid Energy Source Fed Fuzzy-Based SVPWM for 5-Level NPC Inverter with Grid Connected System

This paper presents the fuzzy-based Space Vector Pulse Width Modulation (SVPWM) for 5-level Neutral Point Clamped inverter with hybrid energy source fed grid connected system. The proposed scheme is energized using Photovoltaic and Wind energy system combination. The Neural Network-(NN) based Maximum Power Point Tracking algorithm (MPPT) has been implemented to track maximum power under different operating conditions. First, we proposed fuzzy-based SVPWM, which is developed for 5-level NPC inverter to provide voltage and current control, reduced THD, predetermined switching pattern, capacitor voltage unbalance minimization and maintain good control under nonlinearities and suspicions of PV-Wind energy connected hybrid system. Second, we proposed the inverter output voltage, which has been synchronized with grid connected system using split inductor (SI). The reference voltages for SVPWM implementation were obtained using feedback current control method. Third, we proposed different solar radiations, the proposed system has attained better performance by trailing maximum power from hybrid energy system. The simulation and experimental responses have been validated using Matlab/simulink and FPGA processor.

Artificial Neural Network based SVPWM for Five Level Cascaded H-bridge Inverter fed Grid connected PV System

An Artificial Neural Network (ANN) based Space Vector Pulse Width Modulation (SVPWM) for five level cascaded H-bridge inverter (CHBI) fed grid connected photovoltaic (PV) system. The multilevel inverter topologies are offers better performance compare conventional two level inverter like reduced total harmonic distortion, less electromagnetic interferences and voltage stresses across switches are low. The ANN based SVPWM generates the switching pulses for cascaded H-bridge inverter; it improves the accuracy in reference vectors tuning and identification, which leads to improve the inverter output voltage, better utilization of dc-link voltage and controlled output current. The ANN control makes the implementation of SVPWM becomes simple and minimizes the intricacy in tracking reference vector and calculation of switching time; it is suitable for any type of non-linear systems. This proposed system is energized using PV system and it is boosted using dc-dc boost converter, and the output of CHBI is synchronized with grid connected system using coupled inductor. The simulation and experimental results of ANN based SVPWM for CHBI is verified using simulink-matlab and DSP processor.

Simplified double switching SVPWM implementation for three‐level VSI

A generalised space vector pulse width modulation (SVPWM) framework for the realisation of all double switching states with a memory-optimised method is proposed to reduce the total harmonic distortion (THD) and to provide neutral point voltage balancing for three-level NPC voltage source inverter (VSI). The proposal provides an efficient SVPWM implementationwith reduced hardware requirement and zero increase in software complexity in comparison to the existing schemes. Microcontroller analogue-to-digital converter (ADC) hardware replaces multichannel ADC and associated Field programmable gate array hardware in this proposal. The proposed method follows digital control architecture and eliminates the need to sample phase voltages separately. The proposed algorithm samples rms voltage of one phase and generates eight bit modulation index command by a suitable compensation algorithm. The implemented SVPWM algorithm takes the modulation index command value and generates phase voltage values by multiplying with the stored sine angle values. Gate pulses are generated in the proposed implementation by the hardware pulse width modulation (PWM) block and there is no need for digital-to-analogue converter. The proposed strategy is validated with a fundamental frequency of 50 Hz on a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI using low-cost PIC microcontroller. The superiority of the proposed method lies in providing an efficient three-level SVPWM implementation with reduced THD, neutral point voltage balancing, reduced hardware requirement, small lookup table and zero increase in the software computing overhead.

A Simplified Space Vector Pulse Width Modulation Implementation in Modular Multilevel Converters for Electric Ship Propulsion Systems

The modularity, fault-tolerability, and voltage scalability features allow the modular multilevel converter (MMC) to be a promising topology for modern electric ship applications. Arm voltage and submodule (SM) capacitor voltage balancing controllers with conventional high-frequency modulation schemes are indispensable for reliable and stable operation of an MMC. This requires an additional external arm controller and the control complexity increases for an MMC with a large number of SMs. Alternatively, the space-vector pulse width modulation (SVPWM) schemes provide more freedom in selecting the voltage vectors to achieve multiple objectives, thus eliminating the arm voltage balancing controller. In this paper, a simplified SVPWM implementation for an $n$ -level MMC is proposed. This scheme utilizes all the available switching states and calculates switching timings by mapping to a two-level space-vector structure. The computational burden of the proposed scheme is independent of converter voltage level, therefore it is computationally efficient and well suited to the MMC with any number of SMs. Experimental results are presented to show the performance of an MMC system using the proposed scheme under steady-state, rapid acceleration and speed-reversal conditions.

Application of Barycentric Coordinates in Space Vector PWM Computations

This paper proposes the use of barycentric coordinates in the development and implementation of space-vector pulse-width modulation (SVPWM) methods, especially for inverters with deformed space-vector diagrams. The proposed approach is capable of explicit calculation of vector duty cycles, independent of whether they assume ideal positions or are displaced due to the DC-link voltage imbalance. The use of barycentric coordinates also permits a well-defined and universal approach to the problem of identifying the region in which the reference vector is located. It completely avoids the use of angles, trigonometric functions, and inverse trigonometric functions and is chiefly based on matrix operations which are well suited for digital signal processor implementation. The proposed approach is exposed and validated for the special case of three-level neutral-point clamped (NPC) inverter controlled by a discontinuous space-vector PWM.

Combined Reactive Power Injection Modulation and Grid Current Distortion Improvement Approach for H6 Transformer-Less Photovoltaic Inverter

In this paper, a combined reactive power modulation and grid current distortion improvement approach is proposed for an H6 transformer-less full-bridge single-phase photovoltaic (PV) grid-connected inverter. H6 transformer-less inverters with traditional modulation and control strategies may not satisfy the requirement of reactive power compensation or may result in more severe zero-crossing current distortion. Therefore, contrary to the traditional modulation, a novel reactive power injection space vector pulse width modulation (SVPWM) is proposed, which consists of two operation stages—inverter modulation and reactive power modulation. The implementation of SVPWM for reactive power modulation using a digital signal processor is also investigated. Furthermore, to suppress the current zero-crossing distortion in the reactive power injection mode, a global sliding mode function based on the proportion-integration-resonance current controller is designed, and the control law of the global sliding mode is derived. Using the segment modulation and grid current distortion improvement approach, the function of reactive current injection is implemented in commercial PV inverters, and the total harmonic distortion of the grid current is decreased significantly by more than 5% in the low-power segment, under the operating conditions of a lagging or leading power factor of 0.95. The effectiveness and feasibility of the proposed approach are verified through simulation and experiment using a 5-kVA prototype.

Common mode voltage reduction in a three‐to‐five phase matrix converter fed induction motor drive

Multiphase power converters generate common mode voltage due to switching actions of the power switches. The resulting common mode current in multiphase motor drives flow through the bearing and shaft. Continuous flow of common mode current gradually weakens the performance of the drives. A space vector pulse width modulation (SVPWM) technique is developed to reduce Common mode voltage (CMV) in a three-to-five-phase matrix converter-based five-phase induction motor drive system. The principle of CMV reduction lies in the selection of proper space vectors for implementation of SVPWM. The proposed technique achieves reduction in the CMV without affecting other performances, i.e. loss in output voltage, total harmonic distortion in the output voltages and currents. The common mode voltage is reduced by selecting a set of proper zero space vectors and placing them in a suitable position within a switching cycle. Using this approach, CMV is reduced by ~30%. Simulation and experimental results are provided for a five-phase induction motor drive fed using a three-to-five-phase matrix converter.

Space‐vector pulse‐width modulation for multiphase voltage source inverters considering reference order

A multiphase space-vector pulse-width modulation (SVPWM) with switching states selected based on reference order is proposed. The immediate advantages include the great reduction of computational complexity and simple extension to arbitrary prime phase numbers. In the first part, the general switching strategy is derived considering pure sinusoidal references. Though the derived method is based on adjacent space-vector selection, unlike the conventional method, it needs not any information of sector number. Further, the duty ratio can be obtained from the N-phase reference directly without any information of selected switching states. The second part shows that the strategy is applicable to multi-frequency references. By comparing the proposed SVPWM with carrier-based PWM, the implementation of SVPWM becomes quite simple. In simulations and experiments, five different references are applied and the results verify the accuracy of the proposed modulator.

Field programmable gate array implementation of space‐vector pulse‐width modulation technique for five‐phase voltage source inverter

This study analyses a field programmable gate array (FPGA) implementation of space-vector pulse-width modulation (SVPWM) technique for five-phase voltage source inverter (VSI). The five-phase VSIs are dominantly used to supply the fivephase drives that are used for high-power applications. It is necessary to develop an appropriate SVPWM technique for the inverters to provide the required output voltages to five-phase induction motor load. In the proposed work, SVPWM algorithm is described in high-speed integrated circuit hardware description language coding and implemented in an XILINX XC3SD1800A FPGA processor. The relationship between the SVPWM technique for medium, large and combinations of large and medium space vectors for five-phase VSI is analysed. The selection of active space vector and zero vectors is discussed and the possibilities of FPGA implementations are explored. The experimental results with 1 hp five-phase induction motor drive are presented for the different SVPWM techniques. The best SVPWM scheme is identified based on the output voltage and total harmonic distortion.

Analysis of Voltage Source Inverters using Space Vector PWM for Induction Motor Drive

The Adjustable Speed Drives (ADS) are generally used in industry. In most drives AC motors are applied. The standard drives used are Induction Motors (IM) and recently Permanent Magnet Synchronous Motors (PMSM) are also used. Developments in power electronics and semiconductor technology have lead to improvements in power electronic systems. Different circuit configurations namely multilevel inverters have become popular and considerable research interest is generated in them. Variable voltage and frequency supply to AC drives is invariably obtained from a three-phase voltage source inverter. A number of Pulse width modulation (PWM) schemes are used to obtain variable voltage and frequency supply. The most widely used PWM schemes for three-phase voltage source inverters are carrier-based sinusoidal PWM and space vector PWM (SVPWM). There is an increasing trend of using SVPWM because of their easier digital realization and better DC bus utilization. This paper proposes SVPWM implementation of an Induction motor. The model of a three-phase voltage source inverter is discussed based on space vector theory. Simulation results are obtained using MATLAB/Simulink environment.

Implementation of a Neural-network-based Space-vector Pulse-width Modulation for a Three-phase Neutral-point Clamped High-power Factor Converter

In this article, an artificial neural-network-based implementation of space-vector pulse-width modulation of a three-phase neutral-point clamped bidirectional converter with improved power quality is proposed. The neural-network-based controller offers the advantage of very fast implementation of the space-vector pulse-width modulation algorithm. This makes it possible to use an application-specific integrated circuit chip in place of a digital signal processor. The proposed scheme employs a three-layer feed-forward neural network, which receives the command voltage and angle information at the input and generates symmetrical pulse-width modulation waves for three phases of the converter with the help of a single timer and some simple logic circuits. The neural-network-based modulator distributes the switching states in such a way so as to balance the neutral-point voltage. The data to be used to train the network by a back-propagation algorithm are generated by simulating the conventional space-vector modulation-based converter for simulation and by experimentally running the space-vector modulation-based converter using a digital signal processor for experimentation. The performance of a neutral-point clamped bidirectional rectifier has been evaluated with the artificial neural-network-based modulator. The simulation results obtained are validated experimentally using a digital signal processor (DS1104) of dSPACE (dSpace, Germany). The results obtained show an excellent performance of the neural-network-based modulator.

Fuzzy logic control of a space-vector PWM current regulator for three-phase power converters

This paper presents a fuzzy logic implementation of space-vector pulse-width modulation (PWM) for three-phase power converters. The conventional space-vector PWM current regulator implementation is generally computationally complex. The fuzzy logic controller implementation relieves the processor of a number of computations, thereby accommodating a less expensive microprocessor. The AC-side rectifier voltages are used as fuzzy-state variables. The fuzzy logic control has two outputs: magnitude and angle of reference voltage. Both conventional space-vector PWM and the fuzzy logic controller are implemented to evaluate performance using a 16-b microcontroller (68HC16). Experimental results are provided for both controllers at the same operating point, where the power drawn by the load is about 3 kW. The fuzzy logic controller reduces the computational burden on the processor by about 30%.