Space-modulated Junction Termination Extension Research Articles

Expanding the dose window of step-etched space-modulated JTE for ultrahigh voltage 4H-SiC devices

A step-etched space-modulated junction termination extension (SE-SM-JTE) is proposed for ultrahigh voltage (≥10 kV) 4H-SiC devices in this work. The proposed structure creates a stepped effective JTE dose profile by introducing the step etching into space-modulated JTE (SM-JTE), which shows great merits in the compromises of the JTE dose window, termination efficiency, termination area, and the complexity of the fabrication process. According to the TCAD simulation results, the SE-SM-JTE with a length of 300 μm (3 times the drift layer thickness) obtains a wide implantation dose window of ±47 % above 12 kV, achieving a wide tolerance to JTE dose and surface fixed charge. The maximum breakdown voltage (BV) of the proposed SE-SM-JTE is 13.8 kV, exhibiting a termination efficiency of 92 %. Moreover, the proposed JTE structure requires only a single ion implantation and subsequent two etchings, which facilitates the fabrication feasibility in ultrahigh voltage 4H-SiC devices.

A Compact Trench-Assisted Space-Modulated JTE Design for High-Voltage 4H-SiC Devices

This article proposes a compact trench-assisted space-modulated junction termination extension (TSM-JTE) design for high-voltage 4H-silicon carbide (SiC) devices. In this design, trench structures are introduced into the JTE region to effectively split the termination region into three functional zones. The proposed termination structure is cost effective in terms of the chip area it occupies; for devices rated at 10 kV, the termination structure extends the edge of the device by only 250 μm. Requiring only one implant, it is relatively cheap to fabricate, while a wide implantation dose window endures that is relatively insensitive to variations in dose that may occur during processing. The same advantages occur at 20 kV, the TSM-JTE proving to have the best tradeoff between maximum breakdown voltage and implantation window, compared with other single implant termination designs, achieving this in 500 μm of termination length. At 3.3 kV, a 110-μm TSM-JTE retains its advantages over the other JTE designs, but floating field rings are expected to consume less area, though this is not the case at the higher voltages.

High-Performance GaN Vertical p-i-n Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge Termination

In this work, we develop highly efficient ET schemes based on a selective-area processing methodology that can effectively stymie device leakage, resulting in reliable device operation. In particular, we demonstrate plasma-assisted molecular-beam epitaxy (PAMBE) facilitated silicon nitride shadowed selective-area growth (SNS-SAG) technique, capable of producing smooth GaN interfaces and sidewalls as an enabling technology for high-performance vertical GaN power devices. SNS-SAG is shown to reduce leakage current by at least four orders of magnitude compared to a dry etched device. Floating guard ring (FGR) and junction termination extension (JTE) based ET designs for GaN p-i-n diodes for punchthrough operation have been simulated and analyzed in order to develop SNS-SAG compatible space-modulated junction termination extension (SM-JTE) schemes capable of achieving maximum reverse blocking efficiency >98% while maintaining a wide doping window of up to $\sim \,\,5\times 10^{17}$ cm−3 at a minimum reverse blocking efficiency of ~ 90% extending well into high 1017cm−3 range ( $\sim \,\,8\times 10^{17}$ cm−3). In conjunction with the proposed SNS-SAG technique, SM-JTE schemes have the prospects to offer reliable GaN vertical power device operation.

Design and fabrication of 10-kV silicon–carbide p-channel IGBTs with hexagonal cells and step space modulated junction termination extension**Project supported by the National Basic Research Program of China (Grant No. 2015CB759600), the Science Challenge Project, China (Grant No. TZ2018003), the National Natural Science Foundation of China (Grant Nos. 61474113, 61574140, and 61804149), the Beijing NOVA Program, China (Grant Nos. 2016071 and

10-kV 4H–SiC p-channel insulated gate bipolar transistors (IGBTs) are designed, fabricated, and characterized in this paper. The IGBTs have an active area of 2.25 mm2 with a die size of 3 mm × 3 mm. A step space modulated junction termination extension (SSM-JTE) structure is introduced and fabricated to improve the blocking performance of the IGBTs. The SiC p-channel IGBTs with SSM-JTE termination exhibit a leakage current of only 50 nA at −10 kV. To improve the on-state characteristics of SiC IGBTs, the hexagonal cell (H-cell) structure is designed and compared with the conventional interdigital cell (I-cell) structure. At an on-state current of 50 A/cm2, the voltage drops of I-cell IGBT and H-cell IGBT are 10.1 V and 8.3 V respectively. Meanwhile, on the assumption that the package power density is 300 W/cm2, the maximum permissible current densities of the I-cell IGBT and H-cell IGBT are determined to be 34.2 A/cm2 and 38.9 A/cm2 with forward voltage drops of 8.8 V and 7.8 V, respectively. The differential specific on-resistance of I-cell structure and H-cell structure IGBT are and , respectively. These results demonstrate that H-cell structure silicon carbide IGBT with SSM-JTE is a promising candidate for high power applications.

Optimization of junction termination extension for ultrahigh voltage 4H-SiC planar power devices

Numerical simulations on the optimization of junction termination extension (JTE) have been performed. Various termination techniques have been applied and simulated in this paper, such as single-zone JTE (S-JTE), multi-zone JTE (M-JTE), and space-modulated JTE (SM-JTE). A completely novel and efficient method is demonstrated in this paper to determine total length of SM-JTE, and it is verified through simulation results. The simulation results show that the SM-JTE could provide a protection efficiency (defined in Section ) of 95.2%, which is much higher than that of M-JTE (82.4%) and S-JTE (64.7%). Based on the fabricated MOSFETs, the interface charge density is extracted and the approximate range of charge density has been determined. The influences of different interface charge densities have been investigated for the three termination techniques respectively. According to the previous reports, the JTE is quite sensitive to the implanted dose, so the blocking capability of each termination structure with different implanted doses is also simulated. The results show that when interface charge is considered, the SM-JTE always shows an enormous advantage over the other two junction termination structures, however the interface charge densities varied. The space-modulated JTE is also applicable to the power planar devices such as MOSFETs and IGBTs, which would provide a very promising lower fabrication cost.

4H-SiC 소자의 JTE 구조 및 설계 조건 변화에 따른 항복전압 분석

Silicon Carbide(SiC) has large advantage in high temperature and high voltage applications because of its high thermal conductivity and large band gap energy. When using SiC to design power semiconductor devices, edge termination techniques have to be adjusted for its maximum breakdown voltage characteristics. Many edge termination techniques have been proposed, and the most appropriate technique for SiC device is Junction Termination Extension(JTE). In this paper, the change of breakdown voltage efficiency ratio according to the change of doping concentration and passivation oxide charge of each JTE techniques is demonstrated. As a result, the maximum breakdown voltage ratio of Single Zone JTE(SZ-JTE), Double Zone JTE(DZ-JTE), Multiple Floating Zone JTE(MFZ-JTE), and Space Modulated JTE(SM-JTE) is 98.24%, 99.02%, 98.98%, 99.22% each. MFZ-JTE has the smallest and SZ-JTE has the largest sensitivity of breakdown voltage ratios according to the change of JTE doping concentration. Additionally the degradation of breakdown voltage due to the passivation oxide charge is analyzed, and the sensitivity is largest in SZ-JTE and smallest in MFZ-JTE, too. In this paper, DZ-JTE and SM-JTE is the best efficiency JTE techniques than MFZ-JTE which needs large doping concentration in short JTE width.

Ultrahigh-Voltage SiC p-i-n Diodes With Improved Forward Characteristics

Silicon carbide (SiC) p-i-n diodes having five different n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> -layer (i-layer) thicknesses from 48 to 268 μm are fabricated. The forward characteristics of SiC p-i-n diodes are significantly improved by carrier-lifetime enhancement. After this improvement, the differential on-resistance is inversely proportional to the square root of current density for all the diodes with different thicknesses of n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> -layer. As a result, the forward current density-voltage characteristics can be approximately expressed by a parabolic function, as in the case of Si p-i-n diodes. Using a 268-μm-thick n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> -layer, the lifetime enhancement, and an improved space-modulated junction termination extension structure, a very high blocking voltage over 26.9 kV and low differential on-resistance of 9.7 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> are achieved.

4H-SiC Diode Avalanche Breakdown Voltage Estimation by Simulation and Junction Termination Extension Analysis

This paper presents and compares different avalanche breakdown voltage estimation methods in 4H-SiC (silicon carbide) using finite element simulation results on Schottky diode. 4H-SiC avalanche breakdown voltage and depletion width estimated with Baligas equations have shown to be higher than other estimation techniques and simulation results, especially for voltages higher than 5kV. This paper discusses the impact of choosing different junction termination extension (JTE) structures on two-dimensional junction curvature effects and electric field crowding for Schottky diodes Space-Modulated JTE (SMJTE) structure with optimum JTE dose and dimension could achieve up to 90% of the parallel plane breakdown voltage. For ultra high voltage devices (&gt;15 kV) the SMJTE has significant improvement in terms of breakdown voltage. It also has a wider optimum JTE dose window. For 1 kV device there is not a significant difference in breakdown voltage between JTE and SMJTE structures.

Ultrahigh-Voltage (&gt; 20 kV) SiC PiN Diodes with a Space-Modulated JTE and Lifetime Enhancement Process via Thermal Oxidation

Ultrahigh-voltage SiC PiN diodes with an original junction termination extension (JTE) structure and improved forward characteristics are presented. A space-modulated JTE (SM-JTE) structure was designed by device simulation, and a high breakdown voltage of 26.9 kV was achieved by using a 270 μm-thick epilayer and 1050 μm-long JTE. In addition, lifetime enhancement process via thermal oxidation was performed to improve the forward characteristics. The on-resistance of the SiC PiN diodes was remarkably reduced by lifetime enhancement process. The temperature dependence of the on-resistance was also discussed.

Ultrahigh-Voltage SiC PiN Diodes with an Improved Junction Termination Extension Structure and Enhanced Carrier Lifetime

Ultrahigh-voltage SiC PiN diodes with an improved junction termination extension (JTE) structure and improved forward characteristics are presented in this paper. An improved space-modulated JTE (SM-JTE) structure was designed by device simulation, and a breakdown voltage of over 17 kV was obtained in a wider range of JTE dose with the improved SM-JTE. In addition, a lifetime enhancement process (thermal oxidation) was performed to improve the forward characteristics. The on-resistance of the SiC PiN diodes with the lifetime enhancement process was reduced to 13 mΩ cm2 at 150 °C compared with that of the SiC PiN diodes with the conventional process (32 mΩ cm2).

Defect Electronics in SiC and Fabrication of Ultrahigh-Voltage Bipolar Devices

Fast epitaxial growth, defect reduction, device designing, and process development in SiC toward ultrahigh-voltage (> 10 kV) bipolar devices are investigated. 100~200 um-thick 4H-SiC epilayers with a low background doping concentration in the low 10^{13} cm^{-3} can be grown at a growth rate greater than 50 um/h. Impacts of extended defects on carrier recombination are clarified in photoluminescence mapping measurements. Generation and reduction of Z_{1/2} center, the dominant lifetime killer, are summarized. After Z_{1/2} elimination by thermal oxidation at 1400^{o}C, the carrier lifetime can be enhanced to 25 us or even longer. By utilizing space-modulated junction termination extension, a 21.7 kV PiN diode is demonstrated. Through unique process development, the current gain in bipolar junction transistors is increased to 250~330.

Breakdown Characteristics of 15-kV-Class 4H-SiC PiN Diodes With Various Junction Termination Structures

15-kV-class 4H-SiC PiN diodes with various junction termination structures have been experimentally investigated. Employment of the space-modulated junction termination extension (SM-JTE) and the two-zone JTE have realized a breakdown voltage over 15 kV, corresponding to 93% of the parallel-plane breakdown voltage. The window of the implanted JTE dose to achieve the ultrahigh voltage has been enlarged, which indicates the robustness to the deviation of effective JTE dose. From the comparison of the experimental JTE-dose dependence of breakdown voltage with the numerical device simulation, a shift toward the heavier JTE-dose region was observed. To explain the phenomenon, effects of the charges at the SiO2/SiC interface are discussed.

Space-Modulated Junction Termination Extension for Ultrahigh-Voltage p-i-n Diodes in 4H-SiC

An edge termination method, referred to as space-modulated junction termination extension (SMJTE) combined with a mesa structure, is presented for ultrahigh-voltage p-i-n diodes in 4H-SiC. Numerical device simulations have been performed for over 15-kV-class 4H-SiC p-i-n diodes with the proposed edge termination. The structure exhibits a high breakdown capability with an improved tolerance for the deviation of impurity dose in the JTE region. Unlike conventional multi-implantation, the proposed termination technique utilizes a single-step implantation with a single mask. A desired laterally tapered doping profile is achieved by fragmenting a conventional JTE region using relatively wide spaces. The simple process of the proposed edge termination makes it applicable to fabrication of various high-voltage devices in 4H-SiC.