Source/drain Extension Regions Research Articles

Analysis of gate tunnelling currents in nanoscale metal—oxide—semiconductor field effect transistors (MOSFETs) with SiO2 and high-K gate dielectrics

In this paper, an analytical model for gate tunnelling current has been deployed by solving the Schrödinger equation using the Wentzel—Kramer—Brillouin approximation method for a trapezoidal potential barrier. The gate tunnelling current has been computed for direct tunnelling from channel to gate as well as for tunnelling from source drain extension region to gate. The effect of temperature variation on gate tunnelling current with an SiO2 thickness of 4nm down to 1nm has been studied at various gate voltages. Gate tunnelling in the case of high-K gate dielectrics and high-K stacks has also been analysed. In order to study the effect of temperature on gate tunnelling current in SiO2 and in high-K dielectrics, the related parameters have been modelled based on physics. The effect of variation of substrate doping concentration (Na) on gate tunnelling current in an n-type metal—oxide—semiconductor field effect transistor (n-MOSFET) with SiO2 has also been studied These studies have been used to bring out the design margins available in equivalent oxide thickness and Na.

Investigation of Parasitic Effects and Design Optimization in Silicon Nanowire MOSFETs for RF Applications

The design of silicon nanowire MOSFETs (SNWTs) for RF applications is discussed in this paper based on 3-D simulation, including the impacts of the parasitic capacitances and resistance. The results indicate that large parasitic capacitances are a dominant factor for nanowire structure, which can significantly degrade the ac characteristics of SNWTs. Resistance of the ultranarrow source/drain extension (SDE) regions, which is the main contributor to the total series resistance of SNWTs, is another important factor influencing the device performance. The requirement of contact resistance of source/drain regions in SNWTs is relatively relaxed compared to the SDE regions. Considering the tradeoff between parasitic capacitances and resistance, optimization of the doping profile in SDE regions of SNWTs with 10-nm gate length is further investigated for RF applications.

Silicon–Carbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

We report the first demonstration of n-channel field-effect transistors (N-FETs) with in situ phosphorus-doped silicon-carbon (SiCP) stressors incorporated in the source/drain extension (SDE) regions. A novel process which formed recessed SDE regions followed by selective epitaxy of SiCP was adopted. High in situ doping contributes to low series resistance to channel resistance ratio and is important for reaping the benefits of strain. Substitutional carbon concentration was varied, showing enhanced drive current with increased for comparable off-state leakage, series resistance, and control of short-channel effects. A record high carbon substitutional concentration of 2.1% was achieved. Use of heavily doped silicon-carbon stressor with large lattice mismatch with respect to Si and placed in close proximity to the channel region in the SDE regions is expected to be important for strain engineering in nanoscale N-FETs.

Significance of Gate Underlap Architecture in FinFETs for Low-Voltage Analog/RF Applications

In the present work, we analyze the enormous potential of source/drain extension (SDE) region engineering in FinFETs for Ultra Low-Voltage analog/rf applications. We show that SDE region design can simultaneously improve two key analog figures of merit (FOM) - intrinsic dc gain (AVO) and cut-off frequency (fT) for 60 nm FinFETs operated at low drive current (Ids = 5 µA/µm). The results are analyzed in terms of spacer-to- gradient ratio, a new design parameter for devices with non- abrupt source/drain regions. The present work provides new opportunities for realizing future ultra low-voltage/low-power analog/rf design with nanoscale SDE engineered FinFETs.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain ( A VO) and cut-off frequency ( f T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance ( g m), transconductance-to-current ratio ( g m/ I ds), Early voltage ( V EA), output conductance ( g ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs.

Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> ) and cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T </sub> ) of 25-nm gate-length FinFETs operated at low drain-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> =10 muA/mum). SDE region optimization in 25-nm FinFETs results in exceptionally high values of A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> (~45 dB) and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> (~70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic dc gain (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> ) and cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) for 60 and 30 nm FinFETs operated at low drive current (J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 5 muA/mum). The improved A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio-a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V FB < V G < 0 V and the second for V G < V FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.

Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-κ gate dielectrics

In the present paper, we propose a new scaling theory to model short channel effects (SCEs) in nanoscale double gate (DG) SOI MOSFETs, addressing two important technological issues—source/drain extension (SDE) region engineering and high-κ gate dielectrics. The impact of SDE region engineering through the optimization of lateral source/drain doping gradient and spacer width on SCEs is extensively analysed in DG devices with high-κ gate dielectrics, using the analytical model and 2D device simulations. Novel technology dependent scaling parameters, i.e., spacer-to-gradient ratio (ρ) and effective channel length (Leff), are proposed for source/drain-engineered DG MOSFETs, and their significance in minimizing SCEs in high-κ gate dielectrics is discussed in detail. Results show that the optimal spacer-to-gradient ratio should be increased with the permittivity of high-κ dielectrics in order to maintain SCEs to an acceptable level. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients, high-κ gate dielectrics and effective channel lengths. The present work provides valuable design insights in the performance of nanoscale source/drain-engineered DG SOI devices with high-κ gate dielectrics and serves as an accurate tool to optimize important device parameters aiding technology development.