Source-drain Contacts Research Articles

Gate dielectric scaling of top gate carbon nanoribbon on insulator transistors

The effects of gate dielectric constant and thickness on the performance of top gate carbon nanoribbon on insulator transistors are studied using a π-orbital quantum simulation model. The focus is on both the zero Schottky barrier (SB) source-drain contacts and the metal-oxide-semiconductor field effect transistor (MOSFET)-like doped source-drain contacts. The gate dielectric constant has little effect on the on/off current ratio, channel transconductance gm, and switching performance in SB contact devices. However, the on/off current ratio, the channel transconductance, and the switching performance significantly improve with high-K gate dielectric in doped contact devices. The physics is related to the modulation of the tunnel barrier. In SB contact devices, the on-state current is limited by the SB, and therefore, the improvement in on/off current ratio and transconductance is insignificant. However, the tunnel barrier modulation in the subthreshold regime is similar in both types of contact and the inverse subthreshold slope has similar improvement with high-K gate dielectrics. The unity current gain frequency (fT=gm/2πCg) degrades with high-K gate dielectric in SB contact devices and improves in doped contact devices. This is because the gate capacitance does not change much with dielectric constant and gm has a significant improvement in doped contact devices. The device performance improves with thinner gate oxide. The on/off current ratio and the inverse subthreshold slope scale as square root of oxide thickness.

AlN/AlGaN/GaN MIS‐HEMTs with recessed source/drain Ohmic contact

AbstractAlN/AlGaN/GaN MIS‐HEMTs were grown on 4 inch silicon to suppress the gate leakage and achieve high breakdown. However the drain current density maximum obtained is low (361 mA/mm) for 15 μm MIS‐HEMTs. Since the contact resistance of the Ohmic contacts on the insulating AlN is high (5.1 Ωmm), the thin AlN layer was etched prior to the evaporation of the source‐drain Ohmic contact. Though the recessed Ohmic contact reduced the contact resistance to 2.5 Ωmm there is no improvement in the drain current density. The poor quality of the 2 nm AlN growth on silicon could be the possible reason behind the low drain current density. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Device characteristics of polymer dual-gate field-effect transistors

Dual-gate organic field-effect transistors (OFETs) were fabricated by solution processing using different p-type polymer semiconductors and polymer top-dielectric materials on prefabricated substrates with gold source-drain contacts defined by photolithography. The semiconductors and top dielectrics films were processed from solution by spin-coating and the silver top gate was applied by shadow mask evaporation. The dual-gate OFETs were characterized in double gate mode by sweeping the bottom gate bias from 40 to −50 V while fixing the top gate potentials, and vice versa. We demonstrate that the change in the threshold voltage of the bottom gate depends on the top gate bias with two linear relationships for two different regimes. The interpretations of the results, assuming that the mobilities of the top and bottom channels have similar magnitudes, and that the capacitance of the semiconductor layer is not negligible, indicated two distinct regimes for a dual-gate p-type OFET. 1. When one gate is positive, hence the respective channel is in depletion and no gate screening will occur, while the other gate is in accumulation regime, the field of the positive gate will penetrate to such a large extend that the channel in accumulation will be affected by both gates. 2. When both channels are in accumulation, the charges present in the channels will screen the respective gate potentials, hence both channels will operate individually and no mutual influences are observed. For a dual-gate OFET with its top channel in accumulation, we demonstrate a drop in the transconductance when the bottom gate potential becomes negative. This transition regime between both linear regimes is marked by a drop in the transconductance, where the bottom channel depends on the bottom gate only and the top channel will depend on both gates. The transition regime results from the fact that the charges accumulated in the bottom channel will start to screen the influence of the bottom gate potential on the top channel and the change in overall drain current will depend only on the change of the current of the bottom channel.

Correlation between microstructure, electronic properties and flicker noise in organic thin film transistors

We report on observations of a correlation between the microstructure of organic thin films and their electronic properties when incorporated in field-effect transistors. We present a simple method to induce enhanced grain growth in solution-processed thin film transistors by chemical modification of the source-drain contacts. This leads to improved device performance and gives a unique thin film microstructure for fundamental studies concerning the effect of structural order on the charge transport. We demonstrate that the 1∕f flicker noise is sensitive to organic semiconductor thin film microstructure changes in the transistor channel.

Self-aligned Amorphous Silicon Thin Film Transistors with Mobility above 1 cm2V−1s−1fabricated at 300°C on Clear Plastic Substrates

ABSTRACTWe have developed a fabrication process for amorphous-silicon thin-film transistors (a-Si:H TFTs) on free-standing clear plastic substrates at temperatures up to 300°C. The 300°C fabrication process is made possible by using a unique clear plastic substrate that has a very low coefficient of thermal expansion (CTE < 10ppm/°C) and a glass transition temperature higher than 300°C. Our TFTs have a conventional inverted-staggered gate back-channel passivated geometry, which we designed to achieve two goals: accurate overlay alignment and a high effective mobility. A requirement that becomes particularly difficult to meet in the making of TFT backplanes on plastic foil at 300°C is minimizing overlay misalignment. Even though we use a substrate that has a relatively low CTE, accurately aligning the TFTs on the free-standing, 70-micrometer thick substrate is challenging. To deal with this immediate challenge, and to continue developing processes for free-standing web substrates, we are introducing techniques for self-alignment to our TFT fabrication process. We have self-aligned the channel to the gate by exposing through the clear plastic substrate. To raise the effective mobility of our TFTs we reduced the series resistance by decreasing the thickness of the amorphous silicon layer between the source-drain contacts and the accumulation layer in the channel. The back-channel passivated structure allows us to decrease the thickness of the a-Si:H active layer down to around 20nm. These changes have enabled us to raise the effective field effect mobility on clear plastic to values above 1 cm2V−1s−1

Ion implantation for low-resistive source/drain contacts in FinFET devices

ABSTRACTFinFET is one of the leading candidates to replace the classical planar MOSFET for future CMOS technologies due to the double-gate configuration of the device leading to an intrinsically superior short channel effect (SCE) control. A major challenge for FinFETs is the increase in parasitic source-drain resistance (Rsd) as the fin width is scaled. As fins must be narrow in order to control SCEs, Rsd reduction is critical. This work will deal with the challenges faced in the use of ion implantation for the low-ohmic source-drain contacts. Firstly a new technique to characterize fin sidewall doping concentration will be introduced. We will have a closer look at the Rsd dependency upon fin width for different fin implant conditions and investigate how the implant conditions affect FinFET device performance. It will be shown that the cause of the device degradation upon fin width scaling is related to the fundamental issues of silicon crystal integrity in thin-body Si after amorphizing implant and recrystallization during source-drain activation.

Transparent electronics: Schottky barrier and heterojunction considerations

Transparent electronics employs wide band gap semi-conductors which are transparent in the visible portion of the electromagnetic spectrum for the fabrication of electronic devices and circuits. Current and future transparent electronics applications require the use of wide band gap oxide semi-conductor interfaces as contacts and rectifiers, as well as for passivation and barrier-shaping layers. Modern Schottky barrier and heterojunction theory can be applied to the assessment of such interfaces, and is reviewed for this purpose from a charge transfer, energy band diagram perspective. Ideal interface formation theory is envisaged as originating from Fermi level mediated charge transfer giving rise to a macroscopic interfacial dipole, while non-ideal theory involves charge neutrality level mediated charge transfer giving rise to a microscopic interfacial dipole. This interface formation theory is applied to the problem of indium tin oxide (ITO) – zinc oxide and ITO – tin oxide interfaces, confirming their utility as injecting source-drain contacts in transparent thin-film transistors.

Self-aligned surface treatment for thin-film organic transistors

For organic thin-film transistors where source-drain contacts are defined on the gate dielectric prior to the deposition of the semiconductor (“bottom-contact” configuration), the gate dielectric is often treated with a self-assembled molecular monolayer prior to deposition of the organic semiconductor. In this letter, we describe a method to apply an ultrathin solution-processed polymer layer as surface treatment. Our method is compatible with the use of the bottom-contact configuration, despite the fact that the polymeric surface treatment does not stand a photolithographic step. Furthermore, we show that our surface treatment results in superior transistor performance.

Dynamics of thin-film spin-flip transistors with perpendicular source-drain magnetizations

A ``spin-flip transistor'' is a lateral spin valve consisting of ferromagnetic source-drain contacts to a thin-film normal-metal island with an electrically floating ferromagnetic base contact on top. We analyze the dc-current-driven magnetization dynamics of spin-flip transistors in which the source-drain contacts are magnetized perpendicularly to the device plane by magnetoelectronic circuit theory and the macrospin Landau-Lifshitz-Gilbert equation. Spin-flip scattering and spin pumping effects are taken into account. We find a steady-state rotation of the base magnetization at GHz frequencies that is tunable by the source-drain bias. We discuss the advantages of the lateral structure for high-frequency generation and actuation of nanomechanical systems over recently proposed nanopillar structures.

A fabrication process for a silicon tunnel barrier with self-aligned gate

A process for fabricating a device based on tunneling through a very thin vertical silicon membrane is presented. The process has been developed on a 〈1 1 0〉 oriented silicon wafer using high resolution e-beam lithography and KOH anisotropic etching to define the structure. A single evaporation step allows the fabrication of both the source–drain contacts and a control gate self aligned to the top of the silicon membrane. A vertical silicon membrane with a thickness of 15 nm has been obtained.

Photoresponse of organic field-effect transistors based on conjugated polymer/fullerene blends

Results on photoresponsive organic field-effect transistors (photOFETs) based on conjugated polymer/fullerene solid-state mixtures as active semiconductor layer and poly-vinyl-alcohol (PVA) or divinyltetramethyldisiloxane-bis(benzocyclobutene) (BCB) as gate dielectrics are presented. With LiF/Al top source–drain contacts all devices show dominantly n-type transistor behaviour. Devices fabricated with PVA as gate insulator reveal gate voltage induced saturation upon illumination but low photostability. Contrary, devices fabricated with BCB as gate insulator show transistor amplification in a wide range of illumination intensities. The increase of the drain–source current by more than two orders of magnitudes upon illumination is explained by the generation of a large carrier concentration due to photoinduced charge transfer at the conjugated polymer/fullerene bulk heterojunction upon illumination (photodoping). After illumination, a change of the dark transfer characteristics with respect to the initial transfer characteristics was observed. The initial dark state is achieved either by applying a large negative gate bias or by annealing.

Ambipolar Carrier Transport in Polycrystalline Pentacene Thin-Film Transistors

We have investigated the dependence of polycrystalline pentacene thin-film transistors (TFTs) characteristics on work function of source-drain contact metals. The pentacene TFTs using Mg, Al, Ag, and Au source-drain electrodes showed only p-type characteristics and the field-effect hole mobilities were strongly dependent on their work function. On the other hand, the pentacene TFTs using Ca source-drain electrodes showed typical ambipolar characteristics. The field-effect hole mobility of 4.5 × 10−4 cm2/Vs and field-effect electron mobility of 2.7 × 10−5 cm2/Vs were estimated from saturation currents. Appearance of an electron enhancement mode in pentacene TFTs was ascribed to the lowering of barrier for electron injection at source electrodes.

Ion Shower Doping of Polysilicon Films on Polyethersulfone Substrates for Flexible TFT Arrays

A technique of ion shower doping was performed to form source-drain contacts for polysilicon thin-film transistors (TFTs) on polyethersulfone (PES) substrates. The doped layer was subsequently annealed with an excimer laser to electrically activate the dopant atoms. The doped polysilicon films on the PES substrate showed much higher sheet resistances than those on the glass substrate with the identical doping and activation conditions. Moreover, the plastic substrates is easily heated up and caused a film failure for the prolonged exposure of the ion shower doping. The effective doping time and the resulting ion dose could be increased remarkably by reducing the radio-frequency power as well as by inserting interval pulses for dopants relaxation during the ion doping. As a result, a sheet resistance value as low as 300 ohms/sq. was obtained, which is low enough for a good ohmic contact.

Strained-Silicon on Silicon and Strained-Silicon on Silicon-Germanium on Silicon by Relaxed Buffer Bonding

We report the creation of two novel complementary metal oxide semiconductor (CMOS)-compatible platforms: strained-silicon on silicon (SSOS) and strained-silicon on silicon-germanium on silicon (SGOS). SSOS substrate has an epitaxially defined, strained-silicon layer directly on silicon wafer without an intermediate SiGe or oxide layer. SSOS is a homochemical heterojunction, i.e., a heterojunction defined by strain state only and not by an accompanying compositional change. SGOS has an epitaxially defined SiGe layer between the strained-silicon channel and the Si substrate, which may prove necessary to prevent excessive off-state leakage in metal oxide semiconductor (MOS) devices due to overlap of source-drain contacts and the interfacial misfit array

Carbon nanotube Schottky diode and directionally dependent field-effect transistor using asymmetrical contacts

We demonstrate the fabrication and operation of a carbon nanotube (CNT) based Schottky diode by using a Pd contact (high-work-function metal) and an Al contact (low-work-function metal) at the two ends of a single-wall CNT. We show that it is possible to tune the rectification current-voltage (I-V) characteristics of the CNT through the use of a back gate. In contrast to standard back gate field-effect transistors (FET) using same-metal source drain contacts, the asymmetrically contacted CNT operates as a directionally dependent CNT FET when gated. While measuring at source-drain reverse bias, the device displays semiconducting characteristics whereas at forward bias, the device is nonsemiconducting.

Properties of III-N MOS structures with low-temperature epitaxially regrown ohmic contacts

A significant limitation in the fabrication of III-N MOSFET relates to the formation of ohmic contacts for enhancement-mode MOSFET structures. Unlike existing III-N HFET devices, which include a high free-carrier density two-dimensional electron gas (2DEG) in the semiconductor substrate, a MOSFET in either accumulation or inversion mode require low free-carrier concentrations for the semiconductor channel to have an off-state. The applied gate bias enhances the free-carrier density in the channel, turning on the FET. Unfortunately, a low free-carrier density substrate is problematic for the formation of ohmic contacts, a problem usually dealt with in silicon MOS through self-aligned ion implantation. The high annealing temperatures associated with activating implanted dopants to substitutional sites limits the use of ion implantation for III-N MOSFET fabrication. To overcome this difficulties, selected area epitaxial re-growth of doped III-N materials was developed to form source-drain contacts on otherwise low-doped III-N epitaxial substrates, yielding the needed N+/n−/N+ or N+/p−/N+ structures. Contact re-growth was performed by MOVPE using a silicon nitride dielectric mask defining plasma-etched recesses in the source-drain region. A significant acceleration in the growth rate and surface roughening was observed following re-growth relative to a non-selective area epitaxial growth due to the reduced fill-factor, motivating a general change in MOVPE-operating conditions during re-growth. As the re-growth was intentionally designed to limit the lateral extent of the source-drain regions, the MOVPE re-growth process was performed under conditions limiting lateral overgrowth. III-N MOSFET structures with epitaxial regrown contacts are projected to provide a pathway for low threshold voltage devices suitable for amplifier or logic applications.

Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping

For leading edge CMOS and DRAM technologies, plasma doping (PLAD) offers several unique advantages over conventional beamline implantation. For ultra-low energy source and drain extensions (SDE), source drain contact and high dose poly doping implants PLAD delivers 2–5× higher throughput compared to beamline implanters. In this work we demonstrate process performance and process integration benefits enabled by plasma doping for advanced 65nm CMOS devices. Specifically, p+/n ultra-shallow junctions formed with BF3 plasma doping have superior Xj/Rs characteristics to beamline implants and yield up to 30% lower Rs for 20nm Xj while using standard spike anneal with ramp-up rate of 75°C/s. These results indicate that PLAD could extend applicability of standard spike anneal by at least one technology node past 65nm. A CMOS split lot has been run to investigate process integration advantages unique to plasma doping and to determine CMOS device characteristics. Device data measured on 65nm transistors fabricated with offset spacers indicate that devices with SDE formed by plasma doping have superior Vt roll-off characteristics arguably due to improved lateral gate-overlap of PLAD SDE junctions. Furthermore, offset spacers could be eliminated in 65nm devices with PLAD SDE implants while still achieving Vt roll-off and Ion−Ioff performance at least equivalent to control devices with offset spacers and SDE formed by beamline implantation. Thus, another advantage of PLAD is simplified 65nm CMOS manufacturing process flow due to elimination of offset spacers. Finally, we present process transfer from beamline implants to PLAD for several applications, including SDE and gate poly doping with very high productivity.

Ambipolar injection in a submicron-channel light-emitting tetracene transistor with distinct source and drain contacts

We report on organic light-emitting transistors with a submicron-channel length, gold source, and calcium drain contacts. The respective contact metals allow efficient injection of holes and electrons in the tetracene channel material. Transistor characteristics were measured in parallel with electroluminescence being recorded by a digital camera focused on the transistor channel. In the case of submicron-channel lengths, the transistor source-drain current at higher gate voltages was determined by the source-drain voltage. At larger channel lengths, the source-drain current was limited by the injection of electrons from the calcium contact, as hole ejection to this contact was fully blocked. The hole blocking is explained in terms of a chemical reaction occurring at the Ca/tetracene interface.

Mainstream rapid thermal processing for source–drain engineering from first applications to latest results

Rapid thermal processing (RTP) technology has been commercially available in the semiconductor industry for about 30 years. Already in 1957, e.g., a solar furnace with a parabolic Al reflector was designed. Despite this, it took several decades for RTP of semiconductors to penetrate the market. Over the last decade, RTP has become a mature application. As a replacement of standard furnaces, it provides outstanding ambient control and very short heating cycles with the highest ramp rates for promotion of desired processes such as implant activation, silicide formation or oxide growth while suppressing unintended processes like diffusion or surface degradation. In the field of ultra-shallow junction (USJ) formation, which is necessary to avoid short channel effects arising during continued scaling of CMOS devices, RTP is indispensable. With the introduction of CoSi 2 as the source–drain contact material and its transition to NiSi for future technology nodes, RTP delivers unique benefits in terms of ambient control and single wafer processing capability. In the current paper, we will present the development and potential of RTP throughout this era and show latest results in USJ annealing as well as source–drain contact formation down to the 90 and 65 nm technology node of the ITRS2003, respectively.

Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures.

Substantial effort has been placed on developing semiconducting carbon nanotubes and nanowires as building blocks for electronic devices--such as field-effect transistors--that could replace conventional silicon transistors in hybrid electronics or lead to stand-alone nanosystems. Attaching electric contacts to individual devices is a first step towards integration, and this step has been addressed using lithographically defined metal electrodes. Yet, these metal contacts define a size scale that is much larger than the nanometre-scale building blocks, thus limiting many potential advantages. Here we report an integrated contact and interconnection solution that overcomes this size constraint through selective transformation of silicon nanowires into metallic nickel silicide (NiSi) nanowires. Electrical measurements show that the single crystal nickel silicide nanowires have ideal resistivities of about 10 microOmega cm and remarkably high failure-current densities, >10(8) A cm(-2). In addition, we demonstrate the fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal-semiconductor interfaces. We produce field-effect transistors based on those heterostructures in which the source-drain contacts are defined by the metallic NiSi nanowire regions. Our approach is fully compatible with conventional planar silicon electronics and extendable to the 10-nm scale using a crossed-nanowire architecture.