Source And Drain Research Articles

Effects of Asymmetric Source-Drain Electrodes and Their Modifications on the Operation of Organic Phototransistors

Asymmetric source and drain (S-D) electrodes and their interfacial modifications have significant effects on the charge injection and transport in organic field-effect transistors, however their effects on the operation and performance of organic phototransistors (OPTs) are unknown. Herein, OPTs with symmetric (Ag-Ag, Au-Au) and asymmetric (Au-Ag, Au-bathocuproine (BCP)/Ag, Au/MoO3-BCP/Ag) S-D electrodes were fabricated and their performances were investigated. The results demonstrated that the devices with asymmetric S-D electrodes are superior than their counterparts with symmetric S-D electrodes. Among the three devices with asymmetric S-D electrodes Au-BCP/Ag device exhibits the highest photo responsivity of 36.6 A/W and external quantum efficiency of 7000%, meanwhile Au-BCP/Ag and Au/MoO3-BCP/Ag device exhibit significantly larger specific detectivity than Au-Ag device. The result gives an important guideline for designing high performance OPTs.

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

In this paper, in order to improve the driving ability of vertically-stacked gate-all-around (GAA) Si nanosheets (NSs) devices, a high-efficiency hybrid pattern technique with the SiNx spacer-image transfer (SIT) and conventional photolithography pattern was proposed and implemented to form size-enlarged landing pads (LPs) on nanscale fins at the same time, which increase the volumes of electrical conductance pathway between NS channels and source and drain (SD) electrodes with high process efficiency and compatibility with traditional mass production technology. Due to introduced new structures, the parasitic resistance of the devices is reduced by 99.8% compared with those of w./o. LPs. Therefore, ∼3 times and ∼2 times driving current enhancements for 500 nm gate length n-type and p-type MOSFETs are obtained, respectively. The results indicate the proposed GAA NS FET fabrication process with LPs by high-efficiency hybrid pattern technique a promising solution for improving the device driving ability for stacked GAA Si NSs devices in future.

Ultrashallow Junction (USJ) Fabrication by Advanced Ion Implantation Processes

For advanced CMOS device process, a preamorphization implant (PAI) procedure had been carried on source and drain (SD) lightly doped source and drain (LDD), heavily doped source and drain (HDD), and contact implants before an ultralow energy (ULE) beamline (BL)-based implant to depress the channeling effect for lower OFF-current and short channel effect (SCE). One-step plasma doping (PLAD) was utilized to replace this two-step BL implant process for the pMOS device because PLAD has an in situ real-time controllability for less channeling effect. The PLAD using B <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> gas with ULE high dose regime was utilized for this application. It significantly reduces cost and increases throughput because this one low-cost PLAD module eliminates PAI BL implant. The pMOS devices also exhibit significant performance improvements, including ~30% lower contact resistances ( <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CS</sub> ), similar threshold voltage ( <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and subthreshold voltage (SV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) characteristics, and ~8% higher drive currents (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>DS</b></sub> ) without degrading OFF-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ).

Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications.

In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 °C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the Vth shift as high as about 178 ± 1 mV/pH, which is five times larger than that of the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 °C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications.

Four-terminal polycrystalline Ge1−xSnx thin-film transistors using copper-induced crystallization on glass substrates and their application to enhancement/depletion inverters

Polycrystalline germanium–tin (Ge1−xSnx) thin films with a thickness of 15 nm were grown at 500 °C using Cu-induced crystallization. The films were applied to fabricate four-terminal (4T) thin-film transistors (TFTs) on a glass substrate. The top gate (TG) was fabricated from 30 nm thick SiO2, while the bottom gate (BG) consisted of a double layer of HfO2 and SiO2 with a capacitance equivalent thickness of 16 nm. Aluminum-induced lateral metallization of the source and drain (SD) was implemented to decrease the parasitic resistance of the SD. The Ion/Ioff of the double gate approximately corresponded to 1 × 104. Furthermore, 4T poly-Ge1−xSnx TFTs operated with a field-effect mobility of 20 cm2 V−1 s−1 for the TG drive and 12 cm2 V−1 s−1 for the BG drive at a control gate voltage of 0 V in both cases. A p-channel enhancement/depletion inverter was validated based on the precise control of threshold voltage using a control gate.

Simulation of a high-performance enhancement-mode HFET with back-to-back graded AlGaN layers

A novel three-dimensional hole gas (3DHG)enhancement-mode (E-mode) heterostructure field-effect transistor (HFET) isproposed and investigated. It features back-to-back graded AlGaN (BGA)barrier layers consisting of a positive-graded AlGaN layer and anegative-graded AlGaN layer, which form polarization gradient andsubsequently induce the three-dimensional electron gas (3DEG) and 3DHG inthe positive- and negative-graded AlGaN layers, respectively. The source anddrain are located at the same side of the metal-insulator-semiconductor(MIS) trench gate, and the source is in contact with the HfO$_{2}$ gateinsulator. First, the on-state current is significantly improved owing tothe high-density 3DEG in the positive-graded AlGaN. Next, the verticalconductive channel between the source and 3DEG is blocked by the 3DHG,thereby realizing the E-mode. The threshold voltage ($V_{\rm~th})$ can bemodulated by a partial doping conductive channel. Subsequently, a highbreakdown voltage (BV) is obtained, because the polarization junction formedby the polarization charges assists in depleting the drift region in theoff-state. Next, the BGA-HFET is smaller than the conventional HFET(Con-HFET) owing to the special location of the source. The BV of theproposed HFET sharply increases to 919 V from 39 V of the Con-HFET with thesame gate-drain spacing, and the saturation drain current is increased by103.5%

The Influence of channel length to the characteristics of CuPc based OFET thin films

The main focus of this research is to characterize organic field effect transistor (OFET) thin films based on CuPc with a bottom-contact structure and varied channel length. OFET was prepared by Si substrate cleaning in the ultrasonic cleaner first, then deposition of the source and drain electrodes on the substrate with vacuum evaporation at room temperature, and finally CuPc thin film deposition among the source, drain, and gate electrodes. The distance between source anddrain electrodes is the channel length of the CuPc thin film. In this research, the channel length was varied; 100 μm, 200 μm and 300 μm, with the same active areas of 2.9-3.42 V and different current, IDS. The result showed that the shorter channel length causes, the bigger IDS flowing on the OFET

Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices

We focused on the damage-free monolayer doping (MLD) method starting from a chemical reaction of molecules on Si and Ge surfaces and applied it to 3D MOSFET device fabrication. MLD methods were verified by different material analysis, such as XPS and Raman spectroscopy. For a Si-based FinFET structure, compared to the device with ion implantation, the short channel effect of source and drain (SD) extension regions formed by MLD are improved. The shallower SD extension regions formed by low-temperature microwave annealing (MWA) are expected to the device showing better electrical properties than deeper ones formed by RTA. In addition, formation of the n- and p-type doping in Ge by MLD was also investigated. Even after annealing at 800°C for 300 sec by RTA, the p-type doping still exhibits a low surface doping concentration due to the low diffusion coefficient of B in Ge and surface diffusion limitations at the MLD/Ge interface. By using a combination of RTA and CO2 laser spike annealing (LSA), MLD n-type doping in Ge are formed with junction depths of ≈15 nm, and peak concentration of ≈ 6 × 1020 atoms/cm3. The dopant activation for the MLD-doped channels of Ge junctionless FinFETs (JLFinFETs) is improved after the additional CO2 LSA.

Effect of the interlayer for source-drain electrodes on a solution-processed zinc-tin-oxide TFT

An interlayer was introduced between the source and drain (S-D) electrodes and the semiconductor in a solution-processed zinc tin oxide (ZTO) thin-film transistor (TFT). The ZTO TFT with a MoO3 interlayer of 0.5 nm between the ZTO and the S-D electrodes displayed better properties: a mobility of 5.6 cm2/V s, a threshold voltage (Vth) of −1.3 V and a subthreshold slope of 0.9 V/dec with better bias stability and hysteresis. This improvement is attributed to the MoO3’s reduction to a conductor, MoO2, and to the inter-diffusion of the interlayer between the active channel and the S-D layers, as confirmed by the XPS spectra and by a TEM-EDX analysis, respectively.

Carrier mobility enhancement versus channel direction in highly-doped Si

Carrier mobilities (μ) versus Si channel directions have been studied for boron-, arsenic-, and phosphorus-implanted highly-doped Si (100) which is equivalent to a source and drain (SD) region of MOSFET by using a continuous anodic oxidation technique/differential Hall effect (CAOT/DHE) technique. The results for B-doped Si show that the hole drift mobility along the Si <100> channel direction can be enhanced relative to the Si <110> channel direction by an average of 12%, and nearly 115% near the surface. For As-doped Si the electron drift mobility along the Si <100> channel direction has little to no enhancement compared to the Si <110> channel direction. For P-doped Si, the electron drift mobility along the Si <100> channel direction can be enhanced relative to the Si <110> channel direction by an average of 10%, and as much as 18% near the surface. This study shows for the first time that electron mobility in P-doped Si is enhanced in the Si <100> channel direction, although the enhancement is not as significant as in B-doped Si. The results are qualitatively and semi-quantitatively consistent with the implant species-dependent effective mobility (μeff) behaviors of CMOS device I–V characteristics.

Performance of Organic Field Effect Transistors with Self-Improved Cu/Organic Interfaces

We fabricate pentacene-based organic field effect transistors (OFETs) with Cu as source and drain (S-D) electrodes. The fabricated devices stored for ten hours under ambient atmospheric conditions exhibit superior performance compared with the as-prepared devices. The field-effect mobility increases from 0.012 to 0.03 cm2 V−1 s−1, and the threshold voltage downshifts from –14 to –9 V. The on/off current ratios are close to the order of 104. The improved performance of the stored devices is attributed to the formation of thin Cu oxide at the Cu electrodes/organic interfaces. These results suggest a simple and available way to optimize device properties and to reduce fabrication cost for OFETs.

Study on Light Induced Leakage Current Related to Amorphous Silicon TFT Design

We investigated the effect of amorphous silicon pattern design regarding to light induced leakage current in amorphous silicon thin film transistor. In addition to conventional design, where amorphous silicon layer is protruding outside the gate electrode, we designed and fabricated amorphous silicon thin film transistors in another two types of bottom gated structure. The one is that the amorphous silicon layer is located completely inside the gate electrode and the other is that the amorphous silicon layer is protruding outside the gate electrode but covered completely by the source and drain electrode. Measurement of the light induced leakage current caused by backlight revealed that the design where the amorphous silicon is located inside the gate electrode was the most effective however the last design was also effective in reducing the leakage current about one order lower than that of the conventional design.

Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate

We investigated the low field mobility and short channel characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) on (110) surface Si substrates with various channel directions from the viewpoints of experiment and numerical simulation. We found that the mobility (µ) ratio of (110) substrates to (001) substrates (µ(110)/µ(001)) does not depend on the vertical electric field due to the identical surface roughness for (110) and (001) substrates. We verified mobility enhancement and its channel direction dependence by conducting a detailed carrier transport simulation using a full band model and relaxation time approximation. We obtained good threshold voltage (Vth) lowering characteristics due to the suppression of channeling at the source and drain (SD) extension by implant sequence control. Our results showed that the improvement in propagation delay time (CV/I) and on-current ratio of nMOS to pMOS (Ionn/Ionp) obtained by using an optimized combination of channel directions and a (110) surface Si substrate is attractive for future LSIs down to the sub-100 nm region.

InGaAs/InAlAs HEMTs with extremely low source anddrain resistances

The performance of InP based InAlAs/InGaAs high electron mobility transistors (HEMTs) is often limited by large parasitic source and drain resistances, caused by high contact and sheet resistances in the access regions. The authors demonstrate that a highly conductive cap layer can be seen as an extension of the ohmic contact if a sufficient tunnelling current between cap layer and channel can be achieved. The significantly reduced source and drain resistances lead to excellent DC and RF characteristics with an extrinsic transconductance of 1150 mS/mm and a current cutoff frequency of 206 GHz (L/sub G/=150 nm).