Solution-processed Thin-film Transistors Research Articles

High-performance of low temperature solution-processed P-channel CuGaO thin film transistors

The exploration of p-type metal-oxide semiconductors (MOS) has garnered growing interest, particularly for their potential applications in next-generation optoelectronic devices, display backplanes, and low-power consumption complementary MOS (CMOS) circuits. Here, we introduced low-temperature solution-processed copper gallium oxide (CuGaO) films for p-channel thin-film transistors (TFTs). Hall Effect measurements confirmed the p-type conduction of CuGaO, revealing a conductivity and mobility of 3.76 ×10−2 S/cm and 7.89 cm2V–1s–1, respectively. The p-channel CuGaO-250 TFT demonstrated a field-effect mobility (μFE) of 1.24 cm2V–1s–1, the lowest subthreshold swing (SS) of 519 mV/dec, and an ON/OFF current ratio (ION/IOFF) of ∼104 at a low operating voltage. The notable improvement in TFT performance can be attributed to the quality of the CuGaO-250 film, a smooth surface morphology, and a reduction of interfacial traps between the semiconductor and the gate insulator. Hence, low-temperature fabrication of the p-channel CuGaO TFT holds promise for implementing metal oxide-based TFT and complementary metal oxide semiconductor (CMOS) circuits in next-generation displays.

Functionalized MXene ink enables environmentally stable printed electronics

Establishing dependable, cost-effective electrical connections is vital for enhancing device performance and shrinking electronic circuits. MXenes, combining excellent electrical conductivity, high breakdown voltage, solution processability, and two-dimensional morphology, are promising candidates for contacts in microelectronics. However, their hydrophilic surfaces, which enable spontaneous environmental degradation and poor dispersion stability in organic solvents, have restricted certain electronic applications. Herein, electrohydrodynamic printing technique is used to fabricate fully solution-processed thin-film transistors with alkylated 3,4-dihydroxy-L-phenylalanine functionalized Ti3C2Tx (AD-MXene) as source, drain, and gate electrodes. The AD-MXene has excellent dispersion stability in ethanol, which is required for electrohydrodynamic printing, and maintains high electrical conductivity. It outperformed conventional vacuum-deposited Au and Al electrodes, providing thin-film transistors with good environmental stability due to its hydrophobicity. Further, thin-film transistors are integrated into logic gates and one-transistor-one-memory cells. This work, unveiling the ligand-functionalized MXenes’ potential in printed electrical contacts, promotes environmentally robust MXene-based electronics (MXetronics).

Synaptic plasticity and memory mimicked in solution-processed K-doped CuI thin film transistors

Low-voltage electric double layer p-type thin film transistors (TFTs) were fabricated on glass substrates with copper iodide doped with potassium iodide (Cu0.95K0.05Ix) as the channel and chitosan as the dielectric. Cu0.95K0.05Ix TFTs exhibited Ion/Ioff ratio of 2.5 × 104, subthreshold swing of 30 mV/dec, threshold voltage of 1.34 V, operating voltage of 2 V, and saturation field-effect mobility of 16.6 cm2 V−1 s−1. The relaxation phenomenon induced by ion migration was effectively utilized, enabling Cu0.95K0.05Ix TFTs to simulate various synaptic plasticity functions. When a pulse is applied, the drain current reaches a peak, but it takes more time for the current to return to its equilibrium position after the pulse is removed, demonstrating the short-term memory (STM) characteristics of Cu0.95K0.05Ix TFT. It was observed an increasing trend in excitatory postsynaptic current (EPSC) with enhanced pulse width and amplitude, and when the pulse amplitude increased to −10 V, the TFT transitioned from STM to long-term memory characteristics. Furthermore, the measurement of consecutive EPSC revealed the paired-pulse facilitation (PPF) characteristics, with a gradual decrease in the PPF coefficient as the time interval increased, and a selective stronger response to high-frequency signals. Based on the aforementioned research, by extending the device structure to a dual in-plane-gate structure configuration and applying different pulse voltage sequences on the dual gate, the NOR logic functionality was achieved. The study demonstrates the significant potential of p-type Cu0.95K0.05Ix TFTs in the field of synaptic bionics, simulating human learning and memory, and neural chips.

Facile interfacial defect healing in solution-processed In-Ga-Zn-O thin film transistor through rapid intense pulsed light annealing

We introduce intense pulsed light (IPL) annealing as a versatile and cost-effective interface treatment approach for solution-processed In-Ga-Zn-O thin film transistor, focusing on its potential to improve its operational stability. We fabricate solution-processed IGZO-based thin film transistors (IGZO-TFTs) and systematically investigate the dependence of IPL shot numbers on key parameters that dictate the electrical characteristics of the devices. Under identical positive bias stress (PBS) conditions, we compare the operational stability of IGZO-TFTs treated with IPL annealing during ∼5 min to those subjected to conventional high-temperature thermal processes during 2 h, and reveal that IPL-annealed IGZO-TFTs exhibit superior stability as well as significantly suppressed threshold voltage shifts by ∼22 % (from 3.31 to 2.58 V). To gain deeper insights, we employ photo-excited charge collection spectroscopy analysis, which provides quantitative evidence of the rapid recovery of oxygen vacancies and hydrogen-related interfacial defect states (located at 2.1 ∼ 2.5 eV and near 2.79 eV below conduction band minimum) affecting operational device stability. Our findings underscore the technical advantages of IPL annealing over time-consuming thermal processes, positioning it as a promising method for optimizing IGZO-TFT performance.

Bilayer channel structure to improve the stability of solution-processed metal oxide transistors under AC stress

In this work, we report solution-processed bilayer channel thin film transistors (TFTs) based on solution-processed amorphous oxide semiconductors (AOSs) that fulfill both superb electrical performance and device stability against applied alternating current (AC) drain bias stress. Acceptor-like states generation via hot carrier effect (HCE) is a representative device degradation mechanism suggested for AOS-based TFTs when subjected to AC bias stress, featuring threshold voltage (Vth) shift and on-current (Ion) lowering. As excess electric field and accumulated carriers in the AOS channel cause HCE, alleviating carrier accumulation is a key solution for mitigating HCE. Bilayer channel TFTs comprising two different AOSs could work as a countermeasure to overcome HCE since proper energy band alignment of two channels creates a conduction band difference that act as the energy barrier for carriers. In this regard, we employed amorphous indium-gallium-zinc oxide (IGZO) and zinc-tin oxide (ZTO) as bottom and top layer, respectively, for bilayer channel TFT. Designed bilayer channel showed a conduction band difference of 0.18 eV, and fabricated TFT based on this architecture exhibited high mobility over to 5.9 cm2/Vs with slight Vth shift of 0.1 V and Ion lowering of 1.7% for 1000 s against applied AC stress, demonstrating device stability under AC drain bias stress.

Effect of the gas flow rate in the focused-oxygen plasma treatment of solution-processed indium oxide thin film transistors

In2O3 is a transparent semiconductor layer due to its transparency, high mobility, and solution processability. In this paper, we study the effect of focused oxygen plasma treatment on solution processed indium oxide films annealed at 250 °C and analyze the effect of the gas flow rate. Thin film transistor devices were prepared based on pristine In2O3 films and films treated with oxygen plasma using flow rates of 3, 6, and 9 sccm. The results show that controlling the plasma flow rate can be used to finetune the device characteristics, and the selecting the optimal flow rate is important to improve the electron mobility, threshold voltage, on/off current ratio, and the electrical stability of the devices. The In2O3 TFTs treated at 6 sccm showed the best performance with mobility of 2.19 cm2V−1s−1, threshold voltage of of 4.25 V, and on/off current ratio of 2.13 × 106. The successful fabrication of high-performance, low-temperature solution deposited indium oxide transistors using the focused oxygen plasma treatment for electrical device applications demonstrates the practical potential of this treatment method for future transparent electronics.

Low-Voltage Solution-Processed Zinc-Doped CuI Thin Film Transistors with NOR Logic and Artificial Synaptic Function.

Low-voltage Zn-doped CuI thin film transistors (TFTs) gated by chitosan dielectric were fabricated at a low temperature. The Zn-doped CuI TFT exhibited a more superior on/off current ratio than CuI TFT due to the substitution or supplementation of copper vacancies by Zn ions. The Zn-doped CuI films were characterized by scanning electron microscope, X-ray diffraction, and X-ray photoelectron spectroscopy. The Zn-doped CuI TFTs exhibited an on/off current ratio of 1.58 × 104, a subthreshold swing of 70 mV/decade, and a field effect mobility of 0.40 cm2V-1s-1, demonstrating good operational stability. Due to the electric-double-layer (EDL) effect and high specific capacitance (17.3 μF/cm2) of chitosan gate dielectric, Zn-doped CuI TFT operates at a voltage below -2 V. The threshold voltage is -0.2 V. In particular, we have prepared Zn-doped CuI TFTs with two in-plane gates and NOR logic operation is implemented on such TFTs. In addition, using the ion relaxation effect and EDL effect of chitosan film, a simple pain neuron simulation is realized on such a p-type TFTs for the first time through the bottom gate to regulate the carrier transport of the channel. This p-type device has promising applications in low-cost electronic devices, complementary electronic circuit, and biosensors.

Improvement in Switching Characteristics and Bias Stability of Solution-Processed Zinc-Tin Oxide Thin Film Transistors via Simple Low-Pressure Thermal Annealing Treatment.

In this study, we used a low-pressure thermal annealing (LPTA) treatment to improve the switching characteristics and bias stability of zinc-tin oxide (ZTO) thin film transistors (TFTs). For this, we first fabricated the TFT and then applied the LPTA treatment at temperatures of 80 °C and 140 °C. The LPTA treatment reduced the number of defects in the bulk and interface of the ZTO TFTs. In addition, the changes in the water contact angle on the ZTO TFT surface indicated that the LPTA treatment reduced the surface defects. Hydrophobicity suppressed the off-current and instability under negative bias stress because of the limited absorption of moisture on the oxide surface. Moreover, the ratio of metal-oxygen bonds increased, while the ratio of oxygen-hydrogen bonds decreased. The reduced action of hydrogen as a shallow donor induced improvements in the on/off ratio (from 5.5 × 103 to 1.1 × 107) and subthreshold swing (8.63 to V·dec-1 and 0.73 V·dec-1), producing ZTO TFTs with excellent switching characteristics. In addition, device-to-device uniformity was significantly improved because of the reduced defects in the LPTA-treated ZTO TFTs.

Low-voltage solution-processed P-type Mg-doped CuI thin film transistors with NAND logic function

Low-voltage electric-double-layer (EDL) p-channel Mg-doped CuI thin-film-transistors (TFTs) have been fabricated on glass substrates at low temperatures. Electrical properties of the solution-processed CuI TFTs with different Mg doping concentrations were investigated. It is observed that compared to undoped CuI TFTs and Mg0.1Cu0.9Ix TFTs, Mg0.05Cu0.95Ix TFTs exhibit an excellent current on/off ratio of 1.1 × 105, a steep subthreshold swing of 21.78 mV/dec, a higher saturation field-effect mobility of 0.95 cm2 V−1 s−1, and the threshold voltage of 1.81 V. The high specific capacitance of 4.7 μF/cm2 is obtained in solution-processed chitosan dielectrics; when it was used as the gate dielectric instead of traditional SiO2, the operating voltage of TFTs can be reduced to 2.5 V. It is noteworthy that the NAND logic function has been realized on the dual in-plane-gate structure of such Mg0.05Cu0.95Ix-based TFTs. Finally, the effects of laser (λ = 638 nm) and negative bias stress (NBS) were observed on Mg0.05Cu0.95Ix TFTs. The transfer curves of the TFT drifted positively as the power of the laser progressively increased; the OFF-state current gradually increased as the NBS time became longer. This paper provides an effective way to improve the performance of p-channel CuI TFTs and indicates that Mg0.05Cu0.95Ix as a promising p-type material for next-generation high-performance low-power-consumption logic circuit applications.

Fully solution-processed carbon nanotubes thin film transistors and PMOS inverters on glass substrate

We report fully solution-processed thin film transistors and PMOS inverters fabricated on glass substrates using single-walled carbon nanotubes (SWCNTs) as active semiconducting material. All the electrodes (gate, source, and drain) were inkjet-printed using silver (Ag) as conductive ink. Spin coated poly-4-vinylphenol dielectric was optimized in terms of thickness and heating conditions for solution-processed SWCNTs thin film transistors to achieve a mobility equal to 0.81 cm2 V−1s−1. We will show that, hole traps at the dielectric-semiconductor interface are responsible for the hysteresis in the transfer curve, and controlled by the different sweep rate of the gate field. Drain-current transients under different bias conditions were studied and the increase in current occurs due to slow polarizations of residual dipolar groups in the dielectric. The adopted technology has been exploited to fabricate a PMOS inverter and studied for high gain and noise margin values at the supply voltage, V DD = −40 V.

Solution-processable thin-film transistors from anthradithiophene (ADT) and naphthothiopene (NT) small molecule-based p-type organic semiconductors

Sustainable green electronics is increasingly needed for a multitude of new applications that will fill daily life in the coming decades.

Effect of channel thickness on radiation hardness of solution-processed oxide thin film transistors

The electrical properties of a-ZITO TFTs with different channel thicknesses were characterized under proton irradiation with electrical stress. The device measurements showed stronger radiation-tolerance of oxide TFTs with smaller channel thickness.

Achieving High-Performance Solution-Processed Thin-Film Transistors by Doping Strong Reducibility Element Into Indium-Zinc-Oxide

Achieving High-Performance Solution-Processed Thin-Film Transistors by Doping Strong Reducibility Element Into Indium-Zinc-Oxide

(Invited) High Performance Fully Solution Processed Transistors Towards Flexible Sustainable Electronics

The shift towards a human-centered society promotes greater interconnectedness between people and the digital space. Modern devices such as displays and sensors in which thin-film transistors (TFT) are key materials have crucial roles in the next-generation society because displays are used as both information terminals and interface for human-device interactions while sensors gather data. Furthermore, there is growing interest in neuromorphic devices which aim to mimic the human brain’s efficiency in simultaneously processing and memorizing information to address the von Neumann bottleneck pervasive in modern computing architecture [1]. Amorphous oxide semiconductors (AOS) have gained attention as excellent materials for TFT [2], memory [3], sensing [4], and neuromorphic [5] applications for their superb combination of electrical performance and transparency. Currently, AOS devices are still mainly fabricated using vacuum process. To achieve high throughput and cost-effective production of numerous ubiquitous devices necessary in the next-generation society, an alternative fabrication process is needed.Solution process is an exceptional candidate because of its: (i) efficient production with cost-effective equipment, (ii) large material utilization (low waste) since it can be an additive process compared to vacuum process (high waste), and (iii) low temperature processability for flexible applications in healthcare, energy, and electronics. However, solution process still has major issues such as inferior performance and reliability compared with vacuum process. Several processes have been developed to address these issues but are mostly focused on improving performance and usually limited to a single solution processed device layer – the channel or gate insulator [6]. Thus, many still opt for vacuum process or a single solution processed layer as a compromise. For truly high throughput fabrication, all device layers should be fabricated by solution process. In reality, fully solution-processed TFTs are challenging to fabricate, have dismal performance (mobility (μ) < 1 cm2/Vs), and poor reliability. Therefore, high temperature (>400 °C) process and exotic materials are required for decent μ <10 cm2/Vs which precludes their use in high performance flexible device applications [7].Here, we present how photo-assisted methods through UV treatment and excimer laser annealing (ELA) can selectively transform AOS regions at low substrate temperatures [8]. Consequently, a single AOS film acts as both the semiconductor channel and conducting electrode to realize fully solution processed TFTs with μ of ~40 cm2/Vs (see Fig. 1) [9]. We also show how alternative methods can be used to enhance the performance and stability of fully solution processed TFTs on rigid/flexible substrates. In particular, how low temperature processes such as light, plasma, and material design of functional materials enable high throughput solution processing of flexible electronic devices. AcknowledgmentThis research was supported by JSPS Kakenhi Grant no. 22K14291.

Enhanced Electrical Performance and Stability of Solution-Processed Thin-Film Transistors with In2O3/In2O3:Gd Heterojunction Channel Layer.

The use of the semiconductor heterojunction channel layer has been explored as a method for improving the performance of metal oxide thin-film transistors (TFTs). The excellent electrical performance and stability of heterojunction TFTs is easy for vacuum-based techniques, but difficult for the solution process. Here, we fabricated In2O3/In2O3:Gd (In2O3/InGdO) heterojunction TFTs using a solution process and compared the electrical properties with single-layer In2O3 TFTs and In2O3:Gd (InGdO) TFTs. The In2O3/InGdO TFT consisted of a highly conductive In2O3 film as the primary transmission layer and a subconductive InGdO film as the buffer layer, and exhibited excellent electrical performance. Furthermore, by altering the Gd dopant concentration, we obtained an optimal In2O3/InGdO TFT with a higher saturation mobility (µ) of 4.34 cm2V−1s−1, a near-zero threshold voltage (Vth), a small off-state current (Ioff) of A, a large on/off current ratio (Ion/Ioff) of , a small subthreshold swing (SS), and an appropriate positive bias stability (PBS). Finally, an aging test was performed after three months, indicating that In2O3/InGdO TFTs enable long-term air stability while retaining a high-mobility optimal switching property. This study suggests that the role of a high-performance In2O3/InGdO heterojunction channel layer fabricated by the solution process in the TFT is underlined, which further explores a broad pathway for the development of high-performance, low-cost, and large-area oxide electronics.

Improvement of Electrical Performance in Solution-Processed InZnO Thin-Film Transistor With a Radio Frequency O2 Triggered Multistacked Architecture

A method for radio frequency oxygen (O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) plasma-assisted treatment of indium zinc oxide (IZO) films with a multistacked architecture fabricated by a low-temperature (200 °C) solution process is investigated. We demonstrate that radio frequency O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma-assisted posttreatment technology can improve the mobility and stability of IZO thin-film transistors (TFTs). The activity layers were formed by spin coating and subsequently thermally annealed at a low temperature of 200 °C, followed by O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -plasma posttreatment process, to form the O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> triggered multistacked architecture. The TFT devices plasma-treated for 3 min exhibit improved electrical characteristics, with a mobility of 7.09 ± 0.24 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, an ON OFF ratio of (1.21 ± 1.22) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{{6}}$ </tex-math></inline-formula> , a threshold voltage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-0.22\,\,\pm \,\,0.35$ </tex-math></inline-formula> V, and a subthreshold swing of 0.34 ± 0.02 V/dec. The improved results offered by the O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma treatment led to a higher mobility and ON/ OFF ratio compared to sample device without this process. The successful fabrication of radio frequency O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> triggered multistacked architecture-based IZO TFTs showing the practical potential of high-performance low-temperature solution-processed preparation technology and radio frequency O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma-assisted treatment for electrical device application.

Humidity effect on electrical performance and bias stability of solution-processed In2O3 thin film transistor

ABSTRACT Relative humidity (RH) in storage environment has a great impact on the electrical performance of thin film transistors (TFTs), and the RH is critical for semiconductor manufacturing and device packaging. In this work, solution-processed indium oxide (In2O3) TFT is fabricated, and the electrical performance of the device is investigated after being exposed to various RH conditions. It is found that the threshold voltage (Vth) and the mobility of In2O3 TFT exhibit clear responses to the RH ranging from 23% to 85%. The inherent mechanism about the humidity effect on the electrical performance is elaborated, and this is due to the “donor effect” from the absorbed water molecules. In addition to the effect on Vth and mobility, RH also exhibits a significant effect on the electrical stability of the TFT. The experimental result indicates that the In2O3 TFT exposed to RH <50% exhibits excellent stability with an applied positive bias stressing for 2000s.

Stable and Solution-Processable Cumulenic sp-Carbon Wires: A New Paradigm for Organic Electronics.

Solution-processed, large-area, and flexible electronics largely relies on the excellent electronic properties of sp2 -hybridized carbon molecules, either in the form of π-conjugated small molecules and polymers or graphene and carbon nanotubes. Carbon with sp-hybridization, the foundation of the elusive allotrope carbyne, offers vast opportunities for functionalized molecules in the form of linear carbon atomic wires (CAWs), with intriguing and even superior predicted electronic properties. While CAWs represent a vibrant field of research, to date, they have only been applied sparingly to molecular devices. The recent observation of the field-effect in microcrystalline cumulenes suggests their potential applications in solution-processed thin-film transistors but concerns surrounding the stability and electronic performance have precluded developments in this direction. In the present study, ideal field-effect characteristics are demonstrated for solution-processed thin films of tetraphenyl[3]cumulene, the shortest semiconducting CAW. Films are deposited through a scalable, large-area, meniscus-coating technique, providing transistors with hole mobilities in excess of 0.1cm2 V-1 s-1 , as well as promising operational stability under dark conditions. These results offer a solid foundation for the exploitation of a vast class of molecular semiconductors for organic electronics based on sp-hybridized carbon systems and create a previously unexplored paradigm.

Solution-processed thin film transistors incorporating YSZ gate dielectrics processed at 400 °C

This work investigates a solution process for yttria-stabilized zirconia (YSZ) thin film deposition involving the addition of yttria nanoparticles, at 400 °C, in air. Different yttrium doping levels in the YSZ were studied and a wide range of optical, structural, surface, dielectric, and electronic transport properties were also investigated. An optimum yttrium doping level of 5% mol. resulted in the smoothest films (RRMS ∼ 0.5 nm), a wide bandgap (∼5.96 eV), a dielectric constant in excess of 26, and a leakage current of ∼0.3 nA cm−2 at 2 MV/cm. The solution-processed YSZ films were incorporated as gate dielectrics in thin films transistors with solution-processed In2O3 semiconducting channels. Excellent operational characteristics, such as negligible hysteresis, low operational voltages (5 V), electron mobility in excess of 36 cm2 V−1 s−1, high on/off current modulation ratio on the order of 107, and low interfacial trap density states (&amp;lt;1012 cm−2), were demonstrated. In addition, excellent film homogeneity was achieved over a large area (16 × 16 cm2), with both film thickness and capacitance deviation of &amp;lt;1.2%.

Enhanced current path by circularly and periodically-aligned semiconducting single-walled carbon nanotubes for logic circuit device

Improving the performance of solution-processed single-walled carbon nanotube thin film transistors (SWCNT TFTs) is essential to their wide usage in next generation large-area electronic devices. However, uncontrollable tube-tube junction and random network formation from conventional solution processes of SWCNTs has limited mobility and on-current level of SWCNT TFTs. Herein, we demonstrate a facile method by switching idea of reducing coffee-ring of the conventionally solution-processed or inkjet-printed thin films. Spontaneous coffee-ring formation of the inkjet-printed droplets is found to enhance directional alignment of SWCNTs in the outer rim of the coffee-rings. The evaporation-driven capillary flow toward the rim inside induces migration of SWCNT and thus forms densely aligned SWCNT rings. Periodic connection of such rings can provide high-current path at a given voltage. Therefore, by additionally forming the periodically connected rings on a pre-established random network of SWCNT in channel area of TFTs, we significantly improved the mobility and I on/I off ratio of SWCNT TFTs without degradations in other electrical parameters such as threshold voltage and subthreshold swing. We also demonstrated all-solution-processed inverters with higher voltage-gain in comparison with conventional ones.