Solid-state Device Technology Research Articles

Hydrogen-induced tunable remanent polarization in a perovskite nickelate

Materials with field-tunable polarization are of broad interest to condensed matter sciences and solid-state device technologies. Here, using hydrogen (H) donor doping, we modify the room temperature metallic phase of a perovskite nickelate NdNiO3 into an insulating phase with both metastable dipolar polarization and space-charge polarization. We then demonstrate transient negative differential capacitance in thin film capacitors. The space-charge polarization caused by long-range movement and trapping of protons dominates when the electric field exceeds the threshold value. First-principles calculations suggest the polarization originates from the polar structure created by H doping. We find that polarization decays within ~1 second which is an interesting temporal regime for neuromorphic computing hardware design, and we implement the transient characteristics in a neural network to demonstrate unsupervised learning. These discoveries open new avenues for designing ferroelectric materials and electrets using light-ion doping.

Micro-Transfer Printing for Heterogeneous Integration of GaN and GaAs HEMTs

Here, we use the micro-transfer printing technique to demonstrate the device-level heterogeneous integration of two solid-state RF device technologies on the same interposer: GaN and GaAs high-electron-mobility transistors. The devices are released from their growth substrate using an epitaxial sacrificial layer while a thin polymer adhesion layer facilitates a strong bond between the target substrate and the compound semiconductor devices, allowing for post-transfer microfabrication processing. Transmission electron microscopy reveals no voids at the device/interposer interface and a polymer adhesion layer thickness of 5 ± 2 nm. No significant degradation in dc electrical characteristics is observed after device transfer for either device technology. Improvement in thermal performance of GaN devices was demonstrated when transferred to a diamond substrate, even with the thin polymer adhesion layer at the device/interposer interface, illustrating a pathway for enhanced thermal management for GaN and other high-output-power density semiconductor technologies. The ability to combine various solid-state technologies at the device level with high density provides an approach to meet next-generation demands for RF and mixed-signal circuits.

Design of the 3.7 GHz, 1 kW CW solid state driver for LHCD system of the SST-1 tokamak

Abstract Advances in solid state device technologies have seen its use foray into areas such as microwave heating and powering the RF cavities of an accelerator. This paper explores the possibility of use of a solid state source/driver for current drive systems of tokamaks. The design of a modular solid state source to be used as a driver for klystrons in the LHCD system of SST-1 tokamak is presented. It comprises of solid state power amplifier (SSPA) units, driven by voltage controlled oscillator (VCO) and pre-driver (gain) amplifier. The paper discusses about the design methodology and simulation of these individual components. The component and system level computer simulation based on behavioural and file based model was performed using AWR Microwave Office (MWO) software. The linear and non-linear EM analysis of individual components have been carried out to ascertain its performance. The designed VCO delivers an output power of 20.2 dBm and phase noise of -91.64 dB/Hz (100 KHz offset) at 3.7 GHz. The pre-driver stage (gain amplifier) provides a large signal gain of 15.7 dB and return loss of -14 dB at 3.7 GHz. The individual power amplifier draws a continuous wave (CW) output power of 45.2 dBm for an input power of 35 dBm and efficiency of 56.68%. The system simulation results exhibit around 1 kW of output power in ideal conditions.

Spin-Torque-Based Quantum Fourier Transform

Quantum computing (QC) provides an efficient platform to solve complex problems such as number factoring and searching. The quantum Fourier transform (QFT) is an integral part of quantum algorithms for integer number factoring, phase estimation, discrete algorithms, interchange of position and momentum states, quantum key distribution protocol, multiparty quantum telecommunication, and quantum arithmetic. The theoretical and experimental implementations of QFT on various platforms have been proposed by researchers. Spin-torque-based qubit(s) manipulation is one of the encouraging solid-state device technologies. However, to date, QFT is not realized by spin-torque-based QC architecture. In this article, the spin-torque-based architecture has been modeled with the help of optimized decomposition of quantum circuits for the QFT. Moreover, an optimal-depth Clifford + T gates set-based quantum circuit is utilized to implement the QFT. The performance analysis in terms of fidelity (>99%), magnitude, and phase difference of respective density matrices for different forms of three-qubit QFT provides a novel way of its physical realization to address the complex problems.

Field Induced Ordering of Nanoparticles

Nanoparticles of semiconductors and metals are promising for the implementation of a variety of photonic and electronic devices with new functionalities and improved performance. For the implementation of nanoparticle based devices it is essential that the nanoparticles are electrically isolated from each other, otherwise the benefits such as quantum confinement or Coulomb blockade, can be lost. A convenient way to achieve such isolation is by ordering the nanoparticles in a periodic fashion, which ensures inter-particle separation as well as improvement in reliability and device performance. There is thus significant interest in the fabrication of ordered nanoparticles. For most electronic and photonic devices, it is typically required that the nanoparticle dimensions be in the 1-20 nm range with size variations of 10% or less. Current lithographic techniques are not suitable for the implementation of such nanoparticles, and nonlithographic techniques are typically used for their fabrication. However, many of the nonlithographic techniques are based on natural self-organization processes and suffer from a lack of flexibility or a lack of engineering control. Among the various nonlithographic techniques, the predominant ones are solution based. While such solution based techniques can produce nanoparticles with the required dimensions and size distributions, and in some cases periodicity, they require complex surface passivation involving organic capping molecules. These capping molecules modify the electrical surface properties of the nanoparticles making charge injection/extraction difficult. In addition, the solution based synthesis techniques are not compatible with solid-state device technology, the primary manufacturing process for electronic and photonic devices. The problems associated with solution based methods can be addressed to some extent by using nonlithographic fabrication techniques based on physical vapor deposition such as Stransky-Krastanov growth by epitaxial process. However, most of these techniques have severe constraints in terms of nanoparticle size, material, periodicity and the choice of substrate. A versatile nanofabrication technique that can produce high purity nanoparticles with flexibility in terms of particle size, nanoparticle material, periodicity and the choice of substrate, together with the capability for in-situ deposition of ohmic contact and isolation dielectric materials, will be an important step towards the realization of a variety of nanoparticle based electronic and photonic devices. Our research group has developed a cluster tool system that addresses the above issues. The system consists of a nanoparticle deposition unit, an electron-beam evaporation unit for the deposition of thin films, and a pulsed DC sputtering unit for the deposition of thick layers of metals and insulators. The nanoparticle deposition system is based on sputtering, thus allowing the deposition of nanoparticles of any material that can be sputtered. In addition, nanoparticle deposition can be carried out at room temperature, making it possible to deposit the nanoparticles on a variety of substrates including flexible substrates. Size selection of nanoparticles is achieved by using a quadrupole mass filter with the capability to provide as low as 2% size control. The nanoparticle deposition unit, the electron beam evaporation unit and the DC sputtering unit are all housed inside an ultra-high vacuum chamber to ensure high purity and good surface properties of the nanoparticles. We have used this technique to fabricate nanoparticles of a variety of metals and semiconductors with sizes ranging from 2 nm to 30 nm with less than 5% size variation and demonstrated the viability of the system for the fabrication of nanoparticle based electronic and photonic devices. The nanoparticles deposited in this system are not uniformly distributed, however, most show physical separation from each other. This is due to the charged nature of the nanoparticles creating inter-particle repulsion. In order to create ordered nanoparticles, we have developed a system where the charged nanoparticles can be physically manipulated through the application of an external electric field. The system consists of an electrode mounted on a platform with x,y,z motion and rotation capability. The displacement in the z-direction (vertical) is of nanometer sensitivity which allows the probe to be placed in close proximity to the substrate. The ordering of the nanoparticles is achieved through x,y or rotational scanning of the electrode with an applied voltage, We have demonstrated various ordering of nanoparticles using this technique. We have also extended the technique to order neutral nanoparticles by inducing image charge on the nanoparticles through the electrode and then manipulating the particles. We have also demonstrated that the technique can be used to order magnetic nanoparticles by using a magnetic tip instead of an electrode. In this poster, we will present details of the nanoparticle ordering system, describe the mechanisms affecting the ordering and present experimental results.

Packages for Terahertz Electronics

In the last couple of decades, solid-state device technologies, particularly electronic semiconductor devices, have been greatly advanced and investigated for possible adoption in various terahertz (THz) applications, such as imaging, security, and wireless communications. In tandem with these investigations, researchers have been exploring ways to package those THz electronic devices and integrated circuits for practical use. Packages are fundamentally expected to provide a physical housing for devices and integrated circuits (ICs) and reliable signal interconnections from the inside to the outside or vice versa . However, as frequency increases, we face several challenges associated with signal loss, dimensions, and fabrication. This paper provides a broad overview of recent progress in interconnections and packaging technologies dealing with these issues for THz electronics. In particular, emerging concepts based on commercial ceramic technologies, micromachining, and 3-D printing technologies for compact and lightweight packaging in practical applications are highlighted, along with metallic split blocks with rectangular waveguides, which are still considered the most valid and reliable approach.

Electrical Studies on Parylene-C Columnar Microfibrous Thin Films

Future advances in solid-state device technology are dependent on innovations in multifunctional materials and novel deposition processes and, hence, a wide spectrum of new material compositions and morphologies are being explored. For this study, microfibrous thin films (µFTFs) of Parylene C [1,2] were deposited on top of p-type Si substrates using physicochemical vapor deposition in a PDS2010 Labcoater to form metal-insulator–semiconductor (MIS) and metal–insulator–metal (MIM) capacitor structures utilizing the Parylene-C µFTF as the gate dielectric. Each µFTF was deposited with a collimated vapor flux of Parylene-C monomers inclined at 60° to the substrate plane and had a thickness of about 100 µm. The Parylene-C µFTFs were characterized for electrical properties and dielectric integrity using leakage current, equivalent series resistance and reactance, capacitance measurements at temperatures ranging from –40 °C to 125 °C and frequencies ranging from 1 kHz to 1 MHz, as well as field-emission scanning electron microscopy. The observed variations in leakage current can be explained in terms of transport mechanisms involving thermionic emission and electron hopping. Capacitance and dielectric loss data were analyzed. We found that higher leakage current does not allow for a reliable estimation of the dielectric constant. [1] Pursel, S., Horn, M. W., Demirel, M. C., & Lakhtakia, A. (2005). Growth of sculptured polymer submicronwire assemblies by vapor deposition, Polymer, 46(23), 9544–9548. [2] Chindam, C., Wonderling, N. M., Lakhtakia, A., Awadelkarim, O. O., & Orfali, W. (2015). Microfiber inclination, crystallinity, and water wettability of microfibrous thin-film substrates of Parylene C in relation to the direction of the monomer vapor during fabrication, Applied Surface Science, 345(1), 145–155.

First-Principles Calculation of Dielectric Response in Molecule-Based Materials

The dielectric properties of materials are of fundamental significance to many chemical processes and the functioning of numerous solid-state device technologies. While experimental methods for measuring bulk dielectric constants are well-established, far less is known, either experimentally or theoretically, about the origin of dielectric response at the molecular/multimolecular scale. In this contribution we report the implementation of an accurate first-principles approach to calculating the dielectric response of molecular systems. We assess the accuracy of the method by reproducing the experimental dielectric constants of several bulk π-electron materials and demonstrating the ability of the method to capture dielectric properties as a function of frequency and molecular orientation in representative arrays of substituted aromatic derivatives. The role of molecular alignment and packing density on dielectric response is also examined, showing that the local dielectric behavior of molecular assemblies can diverge significantly from that of the bulk material.

Novel Devices for (Sub)millimeter-Wave Space Applications

Submillimeter-wave space applications require special components for power generation, detection and multiplication. This article presents recent progress in three various solid-state device technologies for submillimeter-wave space instruments: the InP HEMT for ultra-low noise detection at very low power in the IF amplifier, the heterostructure barrier varactor in the frequency multiplier, and the superconducting hot electron bolometer mixer for quantum-limited heterodyne detection above 700 GHz.

Phase diagrams of (gold+binary solder) ternary alloy systems by smith thermal analysis

Application of the Smith thermal analysis method [1] to the experimental determination of ternary alloy phase diagrams is illustrated by reference to a study of the Au−Pb−Bi system. This system, which is of interest in relation to soft-soldered interconnections in solid state device technology, exhibits a ternary eutectic and several transition peritectic reactions.

On some properties and applications of tungsten-alloyed amorphous carbon films

It has been shown that when hydrogenated amorphous carbon films are heavily doped with tungsten they can be made to combine such material properties as relatively high (metallic) electrical conductivity and high mechanical and chemical resistivities (typical of diamond-like carbon). This unique combination of properties, as well as the possibility of producing both electrically conducting and dielectric layers in the same diamond-polymer film structure, creates new perspectives for their application, e.g. in solid state device technology. In this paper we discuss three examples of tungsten-alloyed diamond-like film (DLF) applications. First of all, the characteristics of a DLF-based printing jet head are considered. Secondly, it is shown that there are good prospects for applying the films in the formation of Schottky contacts in integrated circuits (ICs) on GaAs substrates. Finally, some aspects of the localized processing of DLFs of different types by laser irradiation are discussed. There is considerable interest in DLF applications in optical recording, fabrication of photo-masks, and the manufacture of precise resistors, electromechanical sensors and very large-scale (VLS) ICs. Each of these examples not only extends the area of possible DLF applications but also gives us an additional insight into their properties.

TEM study of gold precipitation on defects in silicon

For several decades efforts have been made to investigate the roles of gold in silicon-based solid state device technology. It has been recognized that gold acts as a carrier lifetime controller due to its ability to provide recombination centers when it was introduced into silicon from the surface at high temperature via the so-called kick-out diffusion mechanism. It also has been reported that gold is more soluble in a silicon wafer with high dislocation density, and it can be gettered by diffusing phosphorus or by creating an area of high defect density. However, even though all the previous investigations predict the segregation of gold on defects in silicon it is still unclear how it precipitates on defects. Furthermore, no direct observation of such gold preciptates on defects has been made yet.

High-resolution EM study of the gold silicon interface reaction

Gold occupies a key role in silicon solid state device technology, for contacts and carrier lifetime control. Gold is added to silicon by evaporation onto HF cleaned Si wafers, followed by annealing at high temperature. The Au-Si binary system is a simple eutectic, with very limited terminal solid solubility and no reported stable intermediate compounds. When Si wafers are HF cleaned and exposed to air, even for very short times, a native oxide film a few nm thickness will form, and be interposed between the Si substrate and the evaporated Au layer. The effect of this film on the interface reaction is of interest. Alternatively, conventional surface research on Au/Si interfaces formed by UHV in-situ cleaning, evaporation and annealing provided evidence for an amorphous Au-Si layer and metastable crystalline Au silicides at the position of the original Au/Si interface.

Growth of III–V semiconductors by molecular beam epitaxy and their properties

Advances in solid state device technology in the sixties established III–V materials as a new class of semiconductors for high speed microwave and highly efficient optical devices. Molecular beam epitaxy (MBE) is an extremely versatile thin film technique which can produce single-crystal layers with atomic dimensional controls and thus permit the preparation of novel structures and devices tailored to meet specific needs. Important factors to achieve high quality MBE growth such as in situ analysis, substrate preparations, growth conditions and layer properties are discussed.

Low-pressure chemical vapor deposition for very large-scale integration processing—A review

An overview is presented of low-pressure chemical vapor deposition and its applicability to VLSI processing for depositing thin films of insulators, semiconductors, and metals. The major contributions of low-pressure chemical vapor deposition to VLSI technology are its capability for economically producing films with superior uniformity, high purity, and excellent step coverage-factors essential for achieving the very high device reliability and high product yield required in the manufacturing of VLSI devices. Specific examples from the recent literature are reviewed to exemplify how the technique has been utilized to date in solid-state device technology. Applications of films produced by low-pressure reactive plasma chemical vapor deposition are also included.

Conference Series No 40 Solid State Devices 1977: Nine invited papers presented at the 7th European Solid State Device Research Conference at Brighton 12–15 September 1977

E A Ash (ed) 1978 Bristol and London: Institute of Physics vii + 177 pp price £16.50 The invited papers from this conference survey aspects of present and possible future developments in solid state device technology. On the future direction of silicon devices, Gordon Moore of Intel identifies the driving forces in digital electronics: cost, performance, reliability and new functions.

Solid-state devices and the age of indolence

Solid-state device technology is extending man's capabilities and the subsequent change in manufacturing technology offers a major threat to large segments of existing manufacturing industry, although, simultaneously, the same technology is creating major new markets - many indeed associated with the growing leisure industries. Hence the overall relationship between solid-state device technology and indolence in its widest sense would seem to be: first, current trends in silicon integrated-circuit technology lead inexorably to the need for massive redeployment and retraining of people currently employed in many existing industries; secondly, this same technology is creating many new market and job opportunities, frequently associated with the consumer and leisure industries; and, thirdly, a useful way of forecasting further technical change is to work on the assumption that it will be in such a direction as to make life ‘easier’ for the manufacturer or the user - or both

A Solid-State Regenerative Repeater for Guided Millimeter-Wave Communication Systems

Recent advances in solid-state device technology for generating millimeter waves as well as advances in component design for IF and baseband portions of repeaters have renewed interest in millimeter-wave guided-wave communication systems. This paper describes a 306 Mb/s, all solid-state repeater which has been built using a 1.3-GHz IF and a form of differentially-coherent phase modulation. A signal-to-noise ratio of 13.6 dB is required for an error probability of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−9</sup> (compared with a theoretical value of 13.0 dB for an ideal differentially-coherent phase-modulated system). Sufficient gain for 15-mile repeater spacings (using two-inch circular waveguide) has been obtained with an LSA diode, an IMPATT diode, and a varactor multiplier as the millimeter-wave power source.

An Experimental 224 Mb/s Digital Multiplexer-Demultiplexer Using Pulse Stuffing Synchronization

Solid-state device and circuit technology has advanced to the point where processing of digital signals with bit rates as high as 224 Mb/s may be accomplished. As a specific demonstration of this fact, an experimental mutliplexer-demultiplexer has been developed which combines the following signals into a 224 Mb/s binary pulse train for transmission over a digital transmission network and which furnishes the necessary processing to reconstitute the original signal components: i) A PCM-coded commercial color video signal (111.2 Mb/s) ii) A PCM-coded FDM mastergroup signal (55.6 Mb/s) iii) Two T1 carrier (24 voice channel TDM) signals (1.544 Mb/s each) iv) Word generator signals to occupy the remaining time slots. The line bit rate is derived from and is therefore synchronous with the coded video signal; however, the coded mastergroup and T1 carrier signals are derived from independent clocks. Synchronization of the latter two signal types has been achieved through the use of pulse stuffing synchronization with added-bit synchronization signaling. The ability of a 224 Mb/s buffer memory coupled with a phase-locked loop to attenuate adequately the timing jitter which accumulates in a long digital transmission network has also been demonstrated. All of the experimental results have indicated that the realization of a commercial high-speed digital multiplexer-demultiplexer is feasible.