Solid Diffusion Source Research Articles

On the modelling of silicon wafer doping with phosphorus from a solid planar diffusion source

A model for the phosphorus oxide concentration profile in the gas phase between silicon wafer and solid planar diffusion source has been developed for the case of external-diffusion control of PxOy emission from the source. On the assumption that the uniformity of the doping characteristics across the silicon wafer radius coincides with the concentration uniformity, experimental results available from the literature for the sheet resistance distribution have been interpreted. The model predicts the system behaviour at high temperatures and atmospheric pressure and the uniformity of the sheet resistance in the central part of the silicon wafer much better than that developed for the internal-diffusion control of PxOy emission. The subjects of further experimental research needed for a more profound understanding of the doping process have been defined.

Shallow junction formation by phosphorus diffusion from in situ spike-doped chemical vapor deposited amorphous silicon

Shallow and lateral homogeneous delineated n +p-junctions were formed by utilizing solid source diffusion from a deposited amorphous silicon layer with an in situ imbedded P rich zone. After heat treatment the layer remains flat, surface roughness has found to be less than 3nm. Dopant pile up at the Si-layer/Si-substrate interface has been observed and interpreted based on segregation phenomena. From the time dependence the P segregation pile up has found to be diffusion limited except of a small starting period. The dopant concentration in the Si-substrate drops down over more than 2 orders of magnitude in a thickness range less than 20 nm.

Formation of Raised Source/Drain Junctions by Rapid Thermal Chemical Vapor Deposition

AbstractIn this paper, we present alternative uses of rapid thermal chemical vapor deposition (RTCVD) in forming junctions for the raised source/drain MOSFET. The results will include applications of epitaxial silicon, SixGe1−x and TiSi2 all selectively deposited in dedicated coldwalled, lamp heated high or ultra high vacuum RTCVD reactors. Two general approaches will be considered : 1) ultra shallow junction formation in silicon followed by a selective deposition process to form a raised contact, 2) selective deposition to obtain a layer that can be used as a solid diffusion source and as a sacrificial layer for self-aligned silicide formation. In the first approach, junctions are formed typically by low energy ion-implantation. In this paper, we present rapid thermal vapor phase doping (RTVPD) as an alternative to ion-implantation to form defect free ultra-shallow junctions in Si. The method involves exposing a silicon wafer to a dopant gas (such as B2H6) at a moderate temperature (∼600°C) for a short time and subsequent annealing for drive-in. This is followed by either selective epitaxy and conventional self-aligned TiSi2 formation or selective deposition of a low-resistivity C54 TiSi2 from TiCl4 and SiH4. In the second approach, first, a semiconductor (Si, polysilicon or SixGe1−x) is deposited selectively. If the material is undoped, doping can be achieved by ion-implantation. In-situ doping is also possible as will be shown with p- and n-type SixGe1−x at temperatures as low as 625°C using B2H6 or PH3. The doped layer is then used as a solid diffusion source to form the junctions by out-diffusion. Using these different approaches, we present examples of high quality junctions in Si as shallow as a few hundred angstroms. The techniques are compared based upon their robustness, complexity, equipment and thermal budget requirements.

Low-temperature growth of silicon-boron layer as solid diffusion source for polysilicon contacted p/sup +/-n shallow junction

A new material, Si-B, is proposed as a solid diffusion source for fabrication of poly-Si contacted p/sup +/-n shallow junctions. The junction depth of the Si-B source diode has been measured and compared with that of a BF/sub 2//sup +/-implanted poly-Si source diode. It was found that the Si-B source diode had a much shallower junction and was less sensitive to thermal budget than the BF/sub 2//sup +/ source diode. This was attributed to the smaller surface concentration and diffusivity of boron in the silicon in Si-B source diodes. Regarding electrical characteristics of diodes with a junction depth over 500 /spl Aring/, a forward ideality factor of better than 1.01 over 8 decades and a reverse-current density lower than 0.5 nA/cm/sup 2/ at -5 V were obtained. As the junction depth shrank to 300 /spl Aring/, the ideality factor and reverse current density of diodes increased slightly to 1.05 and 1.16 nA/cm/sup 2/, respectively. These results demonstrated that a uniform ultrashallow p/sup +/-n junction can be obtained by using a thin Si-B layer as a diffusion source.

A model for the concentration profile of PxOy in the interwafer gas phase on phosphorus doping of silicon using a solid planar diffusion source

A mathematical model for the concentration profile of PxOy in the interwafer gas phase on phosphorus doping of silicon using a solid planar diffusion source has been derived for the case of internal-diffusion control of PxOy emission from the source and short time of contact between the wafers and the streaming gas. The model allows us to evaluate the effects of various process parameters on the doping characteristics. Its predictions for the influence of pressure, temperature and gas flow rate on the sheet resistance uniformity correspond to the experimental results reported in the literature.

Solid source diffusion from agglomerating silicide sources. II. Experimental results and analysis

The interface roughness and dopant diffusion behavior of CoSi2 silicide-as-a-diffusion-source (SADS) samples annealed at different temperatures and for different periods of time were examined using secondary ion mass spectrometry, with conditions optimized to characterize the solid source diffusion profile. A convolution/deconvolution methodology was applied to derive the root-mean-square silicide/silicon interface roughness and to correct the dopant profiles. The model which was developed to relate the interface roughness and the sheet resistance increase of the agglomerated silicide films worked quite well over the temperature and time range of interest. The measured activation energies confirmed that silicide roughening and its resistance increase share the same kinetic mechanism. Arsenic implanted CoSi2 samples exhibited a better thermal stability than those implanted with BF2. No obvious enhancement or retardation of boron diffusion was seen, while a transient enhancement of arsenic diffusion was observed, but not as pronounced as previously reported. Furthermore, in cases where dopant is strongly segregated or exhibits a marked step at the silicide/silicon interface, even the convolution/deconvolution technique was not able to adequately determine the actual dopant diffusion.

Evaluation of new high temperature boron solid planar diffusion sources through p-n junction characterization

The electrical characterization of p-n diodes fabricated using a newly developed high temperature (⩾ 1100 °C) boron diffusion source consisting of a homogenous distribution of 9Al 2O 3·2B 2O 3 in a SiC foam substrate was carried out and results were compared with those obtained using commercial sources. Specifically, current-voltage and open circuit voltage decay measurements were performed. The results obtained indicate that devices fabricated from the new high temperature source perform satisfactorily, exhibiting characteristics that are comparable to the characteristics of devices fabricated from the established commercial high temperature boron diffusion sources.

On the mechanism of PxOy emission from a silicon pyrophosphate-containing solid planar diffusion source

It is shown that within the temperature interval 900-1000 degrees C the emission of PxOy from a silicon pyrophosphate-containing solid planar diffusion source can be considered as diffusion controlled. Literature data about the decrease in source mass under thermal treatment can be interpreted by a model assuming PxOy diffusion in a homogeneous plane sheet and oxide evaporation from the sheet surface. On this basis the most probable values for the effective diffusivity coefficient of PxOy in the source at 900 and 1000 degrees C are determined.

Solid source diffusion from agglomerating silicide sources. I. Measurement and modeling

An optimized secondary ion mass spectrometry (SIMS) technique was used to characterize the solid source diffusion of dopants, i.e., arsenic and boron, from agglomerating cobalt disilicide sources. It was found that interface roughness plays a dominant role in determining the dopant profiles observed by SIMS. Double convolution of a step function with an exponential function, which represents the SIMS cascade mixing, and then again with a Gaussian function, which represents the silicide interface roughening, were performed to fit the SIMS silicon signal in the transition region of the silicide/silicon interface. Experimental profiles were then deconvoluted with the same functions to derive the ‘‘true’’ dopant diffusion. This convolution methodology eliminates the broadening factors provided by the measuring instrument and by the sample itself, and therefore results in a more physically meaningful diffusion profile. The broadening of SIMS silicon signal also provides a very precise characterization of the thermal stability of the thin polycrystalline silicide film. An analytical model was established to relate the SIMS silicon broadening and the sheet resistance of the agglomerated silicide film. This model predicts that while the amplitude of the root-mean-square roughening goes as the square root of time, the increase in sheet resistance varies linearly with time, provided that the amplitude of roughening is considerably smaller than the thickness of the silicide film.

Polycrystalline Silicon Layers for Shallow Junction Formation: Phosphorus Diffusion from In Situ Spike-Doped Chemical Vapor Deposited Amorphous Silicon

ABSTRACTShallow and lateral homogeneous delineated n+p-junctions were formed utilizing solid source diffusion from a deposited amorphous silicon layer with an in situ imbedded ultrathin phosphorus-rich zone. SIMS, AES, and TEM investigations were carried out to analyze the dopant behavior in correlation to morphological and structural changes during subsequent heat treatments. After heat treatments up to 950°C the layer remained flat, surface roughness was found to be less than 3 nm. Dopant pile up at the Si-layer/Si-substrate interface was observed and interpreted on the basis of segregation phenomena. From the time dependence the P segregation-pile-up was found to be diffusion limited except for a small starting period. The dopant concentration in the Si-substrate drops down over more than 2 orders of magnitude in a thickness range less than 20 nm.

Study of lateral non-uniformity as a function of junction depth in ultra-shallow junctions and its effect on leakage behavior in as-deposited polycrystalline Si and amorphous Si diodes

Heavily implanted polycrystalline Si films are finding increasing applications as solid diffusion sources, for example, in the formation of ultra-shallow junctions in elevated source/drain metal-oxide-semiconductor field effect transistors and polycrystalline Si emitter bipolar junction transistors. For these applications the dopants are implanted into the polycrystalline Si layer and subsequently diffused into the underlying Si substrate. The diffusion behavior, is however, determined by the evolution of the polycrystalline Si grain microstructure, A large final grain size could lead to laterally more non-uniform and hence leakier junctions. These non-uniformities are lesser for high thermal budget anneals (1100–1150°C, 30 s) than for lower thermal budget anneals (950°C, 30 s) because any doping inhomogeneities in the Si substrate get smeared out as the junction becomes deeper. The junction depth, however, cannot be increased indefinitely from a device viewpoint and a trade-off between leakage current and junction depth has to be made. In this paper, we will study the effect of grain microstructure of ion-implanted as-deposited amorphous Si and as-deposited polycrystalline Si diffusion sources on the diffusion of As and B in the Si substrate, correlate it to the electrical properties of the ultra-shallow junctions formed using this technique.

High energy implants of aluminum in Czochralski and floating zone grown silicon substrates

Aluminum ions at 100 MeV were implanted into floating zone (FZ) and Czochralski (CZ) grown Si substrates. At this energy the implanted ions are located at a depth of about 40 μm so to minimize the influence of the surface on the subsequent thermal treatment. In FZ samples the electrically active dose, as measured by spreading resistance profilometry, is independent of the annealing time at 1200°C, but in the CZ samples it decreases considerably with time. Secondary ion mass spectrometry analysis in CZ samples has revealed the presence of a multipeak structure around the projected range region for both Al and O signals. In the FZ the structure is just detectable. The results imply that the Al-O complex formation is, of course, enhanced by the large content of oxygen but that it is catalyzed by the damage created during the implant. In contrast the carrier profiles coincide in both CZ and FZ substrates doped by predeposition of Al from a solid source and subsequent diffusion; i.e. in damage free samples.

A Novel Implantation Free Raised Source/Drain Mosfet Process Using Selective Rapid Thermal Chemical Vapor Deposition Of In-Situ Boron Doped SixGe1-x

ABSTRACTIn this paper, we report electrical characterization of raised source/drain MOS transistors fabricated using selectively deposited, in-situ boron doped SixGe1-x as a solid diffusion source to form the source/drain junctions. The alloy can be deposited with an enhanced selectivity at temperatures as low as 600°C resulting in an abrupt doping profile at the SixGe1-x/Si interface. After deposition, junctions are formed by diffusion of boron from the deposited layer into the silicon substrate. The selectively deposited alloy can serve as a sacrificial layer for self-aligned silicide formation elimintaing the problem of silicon consumption in the substrate. In this work, selective depositions were performed in a typical cold-walled, lamp heated rapid thermal chemical vapor deposition (RTCVD) system at ∼ 610 °C using SiH2C12, GeH4 and B2H6 as the reactive gases. Using this process, MOS transistors with effective channel lengths down to 0.45 gtm were successfully fabricated.

Estimation of effective diffusion time in a rapid thermal diffusion using a solid diffusion source

Two-step rapid thermal diffusion (RTD) of phosphorus and boron using a solid diffusion source is described. From the application of the Boltzmann-Matano method to SIMS profiles of phosphorus and boron after RTD, it has been found that some additional correction terms to the effective diffusion time must be introduced. In the phosphorus diffusion case, the increment of the effective diffusion time due to the supersaturation of point defects during the cooling cycle is about 3 s. In the case of boron diffusion, the additional effective diffusion time is a strong function of diffusion temperature. This has been explained as the effect of initial growth of the boron-rich layer during the glass-transfer process. The introduction of additional correction terms to the effective diffusion time makes it possible to treat the RTD process in a similar manner to normal diffusion.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Small source/drain metal–oxide-semiconductor field effect transistor using a thermally stable local TiSi2 interconnection

A s_mall s_ource/d_rain c_ontact (SSDC) formation technology has been developed. In the SSDC structure, self‐aligned contacts to small source/drain (S/D) regions can be formed without any contact holes because a local TiSi2 interconnect which extends over isolation fields is directly combined with the whole S/D surface area. It is essential in the SSDC process that the local TiSi2 interconnects are formed from a solid phase reaction of the amorphous‐Si (sputter deposited)/Ti (sputter deposited) bilayer containing a low oxygen concentration. The local TiSi2 interconnect is thermally stable up to 900 °C furnace annealing. This thermal stability allows one to use the TiSi2 layer as a solid phase diffusion source for the S/D formation. Consequently submicron n‐channel metal–oxide–semiconductor field effect transistors with the SSDC structure were fabricated and tested, with a physical gate size of 0.42 μm(length)×2.0 μm(width), and the S/D area was shrunk down to 0.4 μm(length)×2.0 μm(width). The maximum linear transconductance was ∼31 mS/mm.

Phosphorus Doping of Silicon Using a Solid Planar Diffusion Source at Reduced Pressures

A silicon pyrophosphate‐containing solid planar diffusion source has been evaluated for phosphorus doping of silicon at reduced pressures. A reduction in pressure generally results in improvements in the uniformity of doping. At the edges of 3 in. silicon wafers diffused at 1000°C, maximum deviations in sheet resistance are reduced from approximately 15 to approximately 5%, if total pressure is reduced from 1 atm to 5 torr. This improvement is even more significant for diffusion at 900°C, where the maximum deviation is reduced from approximately 100% to approximately 10% by the same reduction in total pressure. The use of a “closed” wafer boat configuration combined with reduced pressure results in further improvement in doping uniformity, as evidenced by a deviation in sheet resistance of approximately 1% for diffusion at 900°C. The use of low pressure leads to decreased doping performance of the source as reflected in thinner doped oxide formation and higher sheet resistance values for diffused silicon wafers. The rate of evaporation of phosphorus oxide from the source is increased nearly one order of magnitude as pressure is reduced from 1 atm to 0.5 torr, leading to reduced lifetime of the source.

Single-Wafer RTCVD of Polysilicon: a Complementary Step in Front-End Integrated Processing

AbstractPolycrystalline silicon is used in the fabrication of integrated circuits in various applications. These include a MOS gate material, bipolar emitter and base contacts, trench refill, complementary material for elevated source / drain structures, solid diffusion source for formation of shallow junctions and the active material in thin film transistors. The deposition of polysilicon as the MOS gate electrode or the bipolar emitter contact follows the most critical processing steps in fabrication of these devices. Maximum reproducibility and highest device performance are achieved when the interfaces between the polysilicon and the underneath substrate are well controlled. This level of control can be obtained by combining the compatible processing steps under a controlled environment. Single-wafer RTCVD of polysilicon was introduced to complement the emerging front-end integrated processing technology for MOS, bipolar and BICMOS devices.

AES Study of Rapid Thermal Boron Diffusion into Silicon from a Solid Diffusion Source in Oxygen Ambient

Rapid thermal diffusion of boron into silicon in an oxygen ambient using a solid diffusion source, BN975, to form shallow p+/n junctions of about 100 nm shows anomalous phenomena in that the sheet resistance of the p+ layer decreases with increasing diffusion time at 1100°C, while at 1000°C, the sheet resistance decreases with time only until 20s and then increases after 20s up to 50s. In order to find the cause of the phenomena, the behavior of boron in the glass layer during the rapid thermal diffusion at 1000° and 1100°C has been examined by Auger electron spectroscopy. It has been found that a boron‐rich layer is formed at the silicon surface for the diffusion in a ambient but not in an ambient. Auger electron spectroscopy results indicate that the boron concentration has a peak inside the glass layer when the diffusion is carried out at 1000°C in an ambient, while for the diffusion at 1100°C in an ambient, the boron peak appears at the silicon surface. The anomalous increase of the sheet resistance for the diffusion at 1000°C in an ambient is explained qualitatively by the position of the boron peak and the oxidation of silicon during the diffusion process.

Comparison of Amorphous and Polycrystalline Silicon Films as a Solid Diffusion Source for Advanced VLSI Processes

AbstractThis paper discusses the diffusion behavior of P, B and As from as-deposited amorphous/ polycrystalline silicon into the underlying Si substrate as a function of RTA/ furnace annealing conditions. The evolution of grain microstructure has been studied in as-deposited amorphous/ polycrystalline silicon to determine the inter-dependency of diffusion behavior and grain microstructure. After 60 s RTA at 1100° C for P doping, the microstructure of asdeposited amorphous silicon is drastically changed by rapid grain growth, whereas it is only slightly changed for asdeposited polysilicon. This leads to formation of deeper junctions for as-deposited polysilicon than for as-deposited amorphous Si. For B doping, there is little difference in the final microstructure between as-deposited polysilicon and as-deposited amorphous silicon after anneal. For low annealing temperatures, the junctions for both amorphous and polysilicon diffusion sources are laterally uniform in spite of local inhomogeneities due to grain boundaries. This is believed to be due to the rapid lateral spread of dopants along the interface prior to indiffusion into the substrate. At high annealing temperatures, a number of dark fringes are observed in the substrate along the interface from Crosssectional Transmission Electron Microscopy (XTEM) micrographs, which are more conspicuous for as-deposited amorphous Si. We believe that these fringes arise from local doping inhomogeneities or lattice strain in the substrate. For 30 s RTA at 1150° C, the native interfacial oxide appears to break up, causing epitaxial alignment of the polysilicon layer with respect to the underlying substrate.

Plasma Etching of Ion Implanted Polysilicon

Dry etching of polysilicon doped with phosphorus by ion implantation was studied using a parallel plate etcher and two different etch chemistries ( and ). These two etch procedures were previously found to result in excellent etching of polysilicon which was doped with phosphorus by solid source diffusion. Large differences in the cross‐sectional profiles of ion‐implanted polysilicon were found while using the two chemistries. chemistry caused sharp notch‐like undercuts, while the chemistry exhibited linewidth loss without any notching. Examples of the cross sections of ion implanted polysilicon are presented in this paper along with a discussion of the possible mechanisms which cause the different cross‐sectional profiles in the two etch chemistries. The notching is explained in terms of the variation in the dopant concentration and in the structure of ion‐implanted polysilicon at different depths. The absence of notching in the cross section of ion‐implanted polysilicon etched in the chemistry is explained by proposing that the interaction of oxygen in the chemistry with the etched surface makes the chemistry less sensitive to the dopant concentration in the etched material. Results of a simple experiment which support the proposed explanation are presented.