Solder Spheres Research Articles

Accelerated Life Tests of Flip-Chips With Solder Bumps Down to 30 μm Diameter

In this study, accelerated life tests with ultra fine-pitch flip-chips with solder bumps down to 30 microns diameter have been performed. Tests commonly used like temperature cycling, high temperature storage, and humidity bias tests are not sufficient for such small packaging feature sizes any more. As solder bump sizes continue to decrease, along with the shrinkage of the solder pads and the scaling of line/space geometries, thermal diffusion has even more impact on reliability and lifetime of the solder connections, and current densities within single solder bumps increase. Therefore, electromigration of flip-chip interconnects is a significant reliability concern, especially when it comes to further miniaturization for high reliability applications. Since electromigration is a function of interconnect sizes and metallurgies, new interconnect developments need to be characterized for electromigration reliability. Flip-chips 10 mm × 10 mm × 0.8 mm in size with a die layout providing a pitch of 100 μm for solder bump sizes of 60 μm, 50 μm, 40 μm, or 30 μm diameter, respectively, have been used [1]. The SnAgCu alloy solder spheres were placed on a NiAu UBM realized in an electroless nickel process [2]. A daisy chain connection is integrated for each of the solder sphere sizes and each chip can separately be connected for online measurements during electromigration or reliability testing. A variety of current density and temperature combinations which is individually adapted to the respective solder sphere diameter has been used. Lifetime data were collected using online measurement through the daisy chains. Cross sectioning has been employed to analyze the influence of thermal diffusion as well as electromigration on the failure mechanism of the highly miniaturized solder joints. A prediction model for flip-chip interconnects with solder spheres down to 30 μm diameter will be outlined using Black’s equation.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

Corrigendum: Three‐Dimensional Fabrication at Small Size Scales

DOI: 10.1002/smll.200901704 Figures 1d, 2d, 5b, and 9a were printed incorrectly in issue 07/10 of Small. The correct figures are given below: The caption for Figure 8a was printed incorrectly; the correct caption is: a) Solder self-assembled plate with kickstands. The polysilicon plate was assembled using an ≈200-µm-diameter solder sphere and is 400 µm wide by 600 µm tall. Reproduced with permission from Reference [159]. Copyright 2000, Elsevier.

Thermomechanically loaded lead-free LGA joints in LTCC/PWB assemblies

Purpose The purpose of this paper is to investigate the feasibility of using land grid array (LGA) solder joints as a second-level interconnection option in low-temperature co-fired ceramic (LTCC)/printed wiring board (PWB) assemblies for telecommunication applications. The characteristic behaviour of two commercial lead-free solder materials (Sn4Ag0.5Cu and Sn3Ag0.5Cu0.5In0.05Ni) in reflow processes and thermal cycling tests are also evaluated. Design/methodology/approach The effect of the reflow temperature profile on voiding in two lead-free solders in LTCC/PWB assemblies was investigated using X-ray and scanning electron microscopy (SEM) investigations. The test assemblies were fabricated and exposed to a temperature cycling test (TCT) in a 0-100°C or −40 to 125°C temperature range. Organic PWB material with a low coefficient of thermal expansion (CTE) was primarily used. In addition, to compare LGA assemblies with low and high global thermal mismatches, an LTCC module/FR-4 assembly was also fabricated and exposed to a TCT in a 0-100°C temperature range. The characteristic lifetime of the test assemblies was determined using DC resistance measurements. The failure mechanisms of the interconnections were verified using scanning acoustic microscopy, SEM and finite element (FE)-SEM investigations. Findings This work showed that the solderability of AgPt-metallized LTCC modules was poor, resulting in excessive voiding. This problem was avoided by using pre-tinned modules. In the test assemblies, the Sn4Ag0.5Cu joints had a lower void content and a higher characteristic lifetime compared with the Sn3Ag0.5Cu0.5In0.05Ni joints. Furthermore, it was observed that the Sn3Ag0.5Cu0.5In0.05Ni joints were more prone to fail along the interface between the Ag3Sn layer and the solder matrix than were the Sn4Ag0.5Cu joints. It was assumed that the observed difference in the primary failure mechanisms resulted in the decreased lifetime duration of the SnAgCu-InNi/Arlon in both temperature cycling conditions. Originality/value The results proved that the solderability of both solders in AgPt-metallized modules in a typical surface mount technology process was poor; however, the solderability of the test modules can be notably enhanced with pre-tinned pads. This work also demonstrated the effect of the metallization/solder pair on the failure mechanisms and failure rate in LTCC/PWB assemblies with LGA joints; the work also proved in the TCT, over a temperature range of 0-100°C, that using the present LGA joints in LTCC/PWB assemblies with a high global thermal mismatch did not increase the lifetime duration of the joints to the preferred level (3,000 cycles), whereas the performance of these joints was adequate in assemblies with a low global thermal mismatch. Moreover, the results indicated that using the LGA joint configuration enhanced the reliability of the LTCC/PWB assemblies compared with similar assemblies with collapsible ball grid array solder spheres.

Effect of Cu concentration, solder volume, and temperature on the reaction between SnAgCu solders and Ni

The interfacial reaction between SnAgCu and Ni is influenced by three important factors, namely, the Cu concentration in solder, solder volume, and temperature. In our previous studies, the first two factors had been investigated individually. In this study, the effects of these three factors are studied concurrently. Three different sizes of solder spheres (300, 500, and 760 μm in diameter) with three different Cu concentrations (0.3, 0.5, and 0.7 wt.%) are used. The aging temperatures are 160 and 180 °C. It is found that as the residual apparent Cu concentration in the solder decreases and the solder volume reduces, the type of intermetallic compound changes from (Cu,Ni) 6Sn 5 to (Ni,Cu) 3Sn 4. This study confirms that the critical Cu concentration decreases as the temperature decreases. In addition, the massive spalling phenomenon, which tends to occur in a liquid–solid reaction, is not observed in the solid-solid reaction.

Fine Feature Solder Paste Printing For Solder Sphere and Solder Trace Manufacturing

Fine round and oblong features were printed using fine solder paste. Diameters and spacings were measured and data was analyzed to show solder feature printing capabilities. The printed features varied from 50 to 450 micron diameters with 50 to 150 micron spacings. Analysis of the solder features showed that printing of round features was possible at every size and spacing, with minimal bridging of the very small spaced features after reflow.

Microstructure Characterization and Creep Behavior of Pb-Free Sn-Rich Solder Alloys: Part I. Microstructure Characterization of Bulk Solder and Solder/Copper Joints

Solders are used as interconnect materials in microelectronic packaging. Traditionally, eutectic and near-eutectic Pb-Sn solder alloys have been used. Due to the toxic nature of lead, environmentally-benign Sn-rich (Pb-free) solders are being developed. In this two part series of articles, we have focused on elucidating the relationship between microstructure and creep behavior of Sn-rich alloys, both in bulk form and at the solder sphere joint level. Part I of our study focuses on a detailed quantitative analysis of the effect of controlled cooling rates on solder microstructures. Bulk solder microstructures from cast bars were compared to smaller solder joint microstructures, reflowed from single solder spheres about 1 mm in diameter. Faster cooling rates resulted in much finer secondary dendrite size and spacing, as well as a much finer distribution of Ag3Sn and Cu6Sn5 particles. The companion article, Part II, provides a unified mechanistic understanding of the creep behavior for the Sn-rich solder alloys, intimately linked to the microstructure characterization work reported in Part I.

Assembly issues with Sn/Ag/Cu bumped flip chips

PurposeThe objective of this research is to address issues that relate to the assembly of Sn/Ag/Cu bumped flip chips.Design/methodology/approachFlip chips bumped with Sn/Ag/Cu bumps were assembled onto different lead‐free surface finishes at lead‐free soldering temperatures. Sensitivity to fluxes, reflow profiles, pad finishes and pad designs were all investigated and the potential consequences for assembly yields were calculated numerically.FindingsSoldering defects, such as incomplete wetting and collapse and poor self‐centring were observed in the assemblies. Defect levels were sensitive to contact pad metallurgy and flux type, but not to flux level and reflow profile within the ranges considered. Owing to a particularly robust substrate‐pad design, defects observed in this work were limited to incomplete wetting and collapse, as well as poor self‐centering.Research limitations/implicationsThe scope of this work is limited to the lead‐free fluxes available at the time of research. A switch to lead‐free solder alloys in flip chip assemblies raises concerns with respect to the compatibilities of materials and the quality of soldering that is achievable. While this may be less of an issue in the case of larger area array components, such as ball grid arrays and chip scale packages, it is more of a concern for applications that use flip chips due to the smaller size of the solder spheres. Assembly yields tend to become more sensitive to the reduced collapse of the joints. More work is essential to investigate the potential benefits of more active lead‐free fluxes, both no‐clean tacky and liquid fluxes, in reducing or eliminating soldering defects.Originality/valueThe paper offers insights into assembly issues with Sn/Ag/Cu bumped flip chips.

Electromagnetic optimization of an RF-MEMS wafer-level package

In this work, we present electromagnetic optimization of a wafer-level package (WLP) intended for RF-MEMS applications. The packaging solution presented is based on a high-resistivity silicon capping substrate containing recesses and copper-filled thru-hole vias. This pre-fabricated capping substrate is first wafer-level bonded to the RF-MEMS device wafer, then populated by solder spheres and finally singulated into individual packages. For the package electrical optimization, Ansoft HFSS™ electromagnetic simulator has been used in order to assess the RF-behaviour of packaged MEMS devices, including losses and mismatch due to inductive and capacitive couplings introduced by the cap. A fully parameterized model of a 50 Ω coplanar waveguide (CPW) including all the degrees of freedom (DoFs) made available by the technological process is presented and extensively exploited for the electromagnetic optimization of the capping structure. Moreover, the measurement data obtained from the fabricated capped and uncapped test structures (50 Q CPWs and shorts) and their comparison with simulations are presented.

Effects of limited cu supply on soldering reactions between SnAgCu and Ni

The volume difference between the various types of solder joints in electronic devices can be enormous. For example, the volume difference between a 760-µm ball grid array solder joint and a 75-µm flip-chip solder joint is as high as 1000 times. Such a big difference in volume produces a pronounced solder volume effect. This volume effect on the soldering reactions between the Sn3AgxCu (x=0.4, 0.5, or 0.6 wt.%) solders and Ni was investigated. Three different sizes of solder spheres (300, 500, and 760 µm in diameter) were soldered onto Ni soldering pads. Both the Cu concentration and the solder volume had a strong effect on the type of the reaction products formed. In addition, (Cu,Ni)6Sn5 massively spalled from the interface under certain conditions, including smaller joints and those with lower Cu concentration. We attributed the massive spalling of (Cu,Ni)6Sn5 to the decrease of the available Cu in the solders. The results of this study suggest that Cu-rich SnAgCu solders can be used to prevent this massive spalling.

Reliability and RF performance of BGA solder joints with plastic-core solder balls in LTCC/PWB assemblies

In this paper board-level reliability of low-temperature co-fired ceramic (LTCC) modules with thermo-mechanically enhanced ball-grid-array (BGA) solder joint structure mounted on a printed wiring board (PWB) was experimentally investigated by thermal cycling tests in the 0–100 °C and −40 to 125 °C temperature ranges. The enhanced joint structure comprised solder mask defined (SMD) AgPt pad metallization, eutectic solder and plastic-core solder balls (PCSB). Similar daisy-chained LTCC modules with non-collapsible 90Pb10Sn solder spheres were used for a reference test set. The reliability of the joint structures was analyzed by resistance measurements, X-ray microscopy, scanning acoustic microscopy (SAM) and SEM/EDS investigation. In addition, a full-wave electromagnetic analysis was performed to study effects of the plastic-core material on the RF performance of the LTCC/BGA package transition up to millimeter-wave frequencies. Thermal cycling results of the modules with PCSBs demonstrated excellent fatigue performance over that of the reference. In the harsher cycling test, Weibull’s shape factor β values of 7.9 and 4.8, and characteristic lifetime θ values of 1378 and 783 were attained for the modules with PCSBs and 90Pb10Sn solder spheres, respectively. The primary failure mode in all test assemblies was fatigue cracking in eutectic solder on the ceramic side.

Experimental wetting dynamics study of eutectic and lead-free solders with various fluxes, isothermal conditions, and bond pad metallizations

Demands on solder bump interconnects have increased in modern electronics. This is characterized by high density, small size, and fine-pitch devices. In solder bump interconnects, solder wetting onto bond pads is the key factor that determines the interconnect process yield and the solder joint reliability. Solder wetting involves various physical phenomena such as surface tension imbalance, viscous dissipation, molecular kinetic motion, chemical reaction, and diffusion. In this paper, an experimental study on solder wetting dynamics will be presented. The effects of solder reflow process parameters and bonding materials will be discussed, as they relate to the physics of solder wetting and ultimately the interconnect process yield and solder joint reliability. The experimental setup consists of a high-speed image acquisition system and a temperature chamber which were used to measure the time dependent behavior of molten solder spheres onto bond pads under an isothermal condition. The solder materials investigated were eutectic tin-lead solder and lead-free 95.5Sn-4.0Ag-0.5Cu solder. The wetting dynamics of the solder materials were investigated on pure Cu bond pads and Cu/Ni/Au bond pads, with several different flux systems, at different environmental temperatures and with various solder sphere sizes. The experimental observations indicate that the wetting dynamics clearly depend on temperature, solder materials, and substrate metallization but do not depend significantly on the flux system or the solder sphere size.

High density and through wafer copper interconnections and solder bumps for MEMS wafer-level packaging

This paper proposes an innovative process combining the electroforming of high-density and through-wafer copper interconnections and solder bumps for advanced MEMS packaging. Vias with the diameter of 30 to 100 μm were etched through on a 4-inch and 550 μm-thick silicon substrate by ICP-DRIE process for an aspect ratio up to 18.3. MRTV1 silicon rubber layer was employed for substrates quickly releasing after copper-interconnections electroforming. Compared to the tedious wet etching or mechanical polishing process, this peel-off relasing process provides a simpler way. After another lithography process, mushroom shape eutecic solder bumps (63Sn/37Pb) were directly electroformed on the top of each copper interconnection with the height of 100 μm, and reflowed at 200 °C for 5 min to form solder spheres. The feasibility of making highly dense and uniform electrical interconncetions has been successfully demonstrated on the wafer with fabricated micro temperature sensors. The estimated resistance for the copper-column of different diameters are characterized lower than 13.1 mΩ and this process provides a bump density up to 9648 interconnects/cm2.

Thermal cycling aging effects on Sn–Ag–Cu solder joint microstructure, IMC and strength

Thermal cycling aging studies on a lead-free 95.5Sn–3.8Ag–0.7Cu solder joint were investigated. Soldered lap joint specimens were fabricated by a solder reflow process using a 95.5Sn–3.8Ag–0.7Cu solder sphere, no-clean flux on FR4 substrate parts. Characterization of the solder joint microstructure, intermetallic compound (IMC) and shear strength was conducted. Studies on the effects of thermal aging on IMC thickness and residual shear strength properties before and after exposure to thermal cycling aging are presented. Temperature cycling aging experiments based on standard thermal cycling (TC) and thermal shock (TS) tests were conducted on the lap joint specimens. IMC growth behavior and shear test results for specimens subject to thermal cycling aging.

Creep deformation behavior of Sn-3.5Ag solder at small length scales

To adequately characterize the behavior of solder spheres in electronic packaging, their mechanical behavior needs to be studied at small-length scales. The creep behavior of single Sn-3.5Ag solder spheres on a copper substrate was studied between 25°C and 130°C using a microforce testing system. In the low-stress regime, the creep stress exponent changed from 6 at lower temperatures to 4 at higher temperatures, indicating creep by dislocation climb. The activation energy for creep was also found to be temperature dependent, and correlated with values for dislocation core diffusion and lattice diffusion in pure tin. A change in the stress exponent with increasing stress was also observed and explained in terms of a threshold stress for dislocation motion, due to the presence of obstacles in the form of Ag3Sn particles.

Underfilling fine pitch BGAs

Fine pitch BGAs and chip scale packages have been developed as an alternative to direct flip chip attachment for high-density electronics. The larger solder sphere diameter and higher standoff of CSPs and fine pitch BGAs improve thermal cycle reliability while the larger pitch relaxes wiring congestion on the printed wiring board. Fine pitch BGAs and CSPs also allow rework to replace defective devices. Thermal cycle reliability has been shown to meet many consumer application requirements. However, fine pitch BGAs and CSPs have difficulty passing mechanical shock and substrate flexing tests for portable electronics applications. The fine pitch BGA used in the study was a 10 mm package with the die wire bonded. The package substrate was bismaleimide-triazine (BT) and the solder sphere diameter was 0.56 mm. Two types of underfill were examined. The first was a fast flow, snap cure underfill. This material rapidly flows under the package and can be cured in five minutes at 165/spl deg/C using an in-line convection oven. The second underfill was a thermally reworkable underfill for those applications requiring device removal and replacement. The paper discusses the assembly and rework process. In addition, liquid-to-liquid thermal shock data is presented along with mechanical shock and flexing test results.

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.

Application of direct strain measurement of fatigue studies in surface solder joints : Yan C. Chan, D.J. Xie, J.K.L. Lai and I.K. Hui. IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, 1995, 18(4), 715

Thermal cycling aging studies on a lead-free 95.5Sn–3.8Ag–0.7Cu solder joint were investigated. Soldered lap joint specimens were fabricated by a solder reflow process using a 95.5Sn–3.8Ag–0.7Cu solder sphere, no-clean flux on FR4 substrate parts. Characterization of the solder joint microstructure, intermetallic compound (IMC) and shear strength was conducted. Studies on the effects of thermal aging on IMC thickness and residual shear strength properties before and after exposure to thermal cycling aging are presented. Temperature cycling aging experiments based on standard thermal cycling (TC) and thermal shock (TS) tests were conducted on the lap joint specimens. IMC growth behavior and shear test results for specimens subject to thermal cycling aging.

Effect of PCB finish on the reliability and wettability of ball grid array packages

Organic protective coatings (OPC) and metallic plating chemistries have emerged as alternatives to traditional hot air solder leveling (HASL) to ensure the solderability of printed circuit boards (PCB). This study examined a number of commercially-available printed circuit board finishes to determine their intrinsic solderability and their effect on the solder joint reliability of ball grid array (BGA) packages. The PCB finishes included OPC (Entek Plus CU-106A and MEC-seal), immersion Au over electroless Ni (LeaRonal, MacDermid, Shipley, and Technique), electroless Pd over Ni, electroless Sn over Cu, immersion Bi over Cu, and HASL. Solderability tests were performed by reflowing 20-mil diameter solder spheres on variously aged test coupons and then quantitatively measuring the area and shape of the solder after cooling. The immersion Au finishes generally exhibited excellent wettability as a function of N/sub 2/ reflow aging as compared with the OPCs and HASL. The Pd-Ni, Sn, and one of the Ni-Au finishes exhibited poor wetting when exposed to an 85/spl deg/C/85% RH environment. Solder joint reliability was measured for a 41 I/O ceramic BGA using cyclic thermal shock (nominally -55-125/spl deg/C) and three point bending. All finishes tested behaved similarly in thermal shock. The Au finishes generally performed worse in three-point bending as compared to OPC and HASL. The wetting and reliability results are correlated with the structure and composition of the finishes and the solder joints.

Finite element analysis for Solder Ball Connect (SBC) structural design optimization

Solder Ball Connect (SBC) is a second-level surface mount electronics packaging technology in which ceramic modules containing one or more chips are joined to a circuit card (FR-4) by means of an array of nonhomogeneous solder columns. These columns consist of a high-temperature-melting 90%Pb/lO%Sn solder sphere attached to the module and card with eutectic solder fillets. The solder structures accommodate the bulk of the strain (which is due to the thermal-expansion mismatch between FR-4 and the 9211 ceramic of the modules) generated during power cycling. If the solder structures are not properly designed, the thermal strain can be a source of premature fatigue failure. In this work, finite element analysis is used to characterize the plastic strains that develop in the SBC interconnection during thermal cycling. Since plastic strain is a dominant parameter that influences low-cycle fatigue, it is used as a basis of comparison for various structural alternatives. Designed experiment techniques are used to systematically evaluate the thermal strain sensitivity to structural variables. Results are used to identify an optimally reliable structure that is robust in terms of assembly-process variables.