Solder Paste Printing Research Articles

A study of SMT assembly processes for fine pitch CSP packages

The surface mount technology (SMT) assembly process for 0.4 mm pitch chip scale package (CSP) components was studied in this work. For the screen printing process, the printing performance of different solder pastes, aperture shapes and sizes was investigated. Square apertures and a fine particle size in the solder paste provided a better paste release. Besides optimising the printing process capability and minimizing the printing defects such as bridging and missing paste, the total volume of solder consisting of the paste and the solder ball has to be considered in order to maximize the final process yield. For the pick & place process, the accuracy required for the placement equipment was determined by studying the self‐alignment of the lead‐free CSPs (with Sn/4.0Ag/0.5Cu balls) during the reflow process using lead‐free Sn/3.9Ag/0.6Cu paste. The components were intentionally misplaced up to ∼50percent off‐pad. After reflow, x‐ray inspection showed that the components had aligned to the pad. By considering the stack‐up of the printed circuit board pad location and size tolerances, the solder paste printing tolerances and the placement tolerances, the required alignment accuracy for the pick & place equipment was established to meet the total process capability requirement.

Allocating solder-paste printing inspection in high-volume electronics manufacturing

The paper describes an optimization model for allocating solder-paste printing inspection that explicitly considers the economic tradeoff between board yield and inspection accuracy. The paper also shows that the use of a heuristic solution method for solving the post-printing inspection allocation model is effective and efficient for high-volume electronics manufacturing. The model has been developed using real production and visual inspection data provided by a high-volume electronics manufacturer located in Huntsville, AL. In addition, randomly generated problems are used to evaluate the performance of the proposed heuristic. Results from a large case study show that when compared with a full post-printing inspection, the heuristic approach provides a solution that can increase the total expected gains by 15%.

Microstructure and creep behaviour of eutectic SnAg and SnAgCu solders

The paper presents creep data, that was gained on specimens of different microstructures. The three specimen types have been flip chip solder joints, pin trough hole solder joints and standard bulk solder specimens. The bulk solder specimen was a dog-bone type specimen (diameter=3 mm, length=117 mm). The pin trough hole solder joint consisted on a copper wire that was soldered into a hole of a double sided printed circuit board (thickness 1.5 mm). The flip chip solder joint specimen consisted of two silicon chips (4 mm × 4 mm), which were connected by four flip chip joints (one on each corner). SnAg and SnAgCu flip chip bumps (footprint 200 μm × 200 μm, joint height 165–200 μm, centre diameter 90…130 μm) were created by printing solder paste. Constant–load creep tests were carried out on all three specimen types at temperatures between 5 and 70 °C. Creep data was taken for strain rates between 10 −10 and 10 −3 s −1. The specimens were tested in “as cast” condition and after thermal storage. The microstructural properties of the bulk specimens and real solder joints were examined using metallographic sectioning, optical microscopy techniques, and SEM-microprobe analysis. The results of the microstructural analysis were related to the investigated mechanical properties of the solders. Models of SnAg3.5 and SnAg4Cu0.5, that can be used with the ANSYS FEM software package, will be presented.

Statistical Monitoring of Solder Paste Printing.

Statistical Monitoring of Solder Paste Printing.

저정밀 X-Y 로봇을 이용한 검사 시스템의 변형된 Hough 변환을 이용한 위치오차보정

The important factors that cause position error in X-Y robot are inertial force, frictions and spring distortion in screw or coupling. We have to estimate these factors precisely to correct position errors, Which is very difficult. In this paper, we makes systems to inspect metal stencil which is used to print solder paste on pads of SMD of PCB with low precision X-Y robot and vision system. To correct position error that is caused by low precision X-Y robot, we defines position error vector that is formed with position of objects that exist in reference and camera image. We apply MHT(Modified Hough Transformation) for the aim of determining the dominant position error vector. We modify reference image using extracted dominant position error vector and obtain reference image that is the same with camera image. Effectiveness and performance of this method are verified by simulation and experiment.

A novel measurement technique for stencil printed solder paste

The printing process is the most critical step in surface mount assembly. To control and monitor printing, complex instrumentation is available for measuring the print consistency. This paper describes a novel robust method, which introduces critical variables defining print quality. Conventional measurement methods include only the volume and average height of solder paste. The limitations of using just these parameters are discussed and a new method is introduced. In our novel approach, the matrix is levelled first to take account of any tilt in the plane of the substrate surface. Then pseudo‐virtual object parameters are calculated. Major attributes of the proposed measurement method is its insensitivity to both the specific location of the printed deposit and the location of a specific defect. This algorithm, coupled with variables defined in the analysis package, delivers a new and flexible approach to the printed media.

Fine pitch stencil printing using enclosed printing systems

Enclosed print heads have recently been developed as an improvement on the traditional squeegee methods for solder paste printing. They offer the opportunity of widening the printing process window and reducing process waste. Consequently, this work was undertaken to evaluate some aspects of enclosed print head printing, and it has been shown to be a robust process. A number of performance factors were established: with increased humidity the paste degradation was limited due to its sealed paste reservoir; the system also permitted successful intermittent printing over a 5 day period; printing is much more tolerant to distorted substrates than some squeegee blades, and hence improves printing on non‐planar surfaces; significant reduction in paste wastage occurs, since paste ageing is reduced.

Open Defects in PBGA Assembly Solder Joints

PBGA has the advantage of being compatible with existing surface-mount process. The eutectic solder balls collapse during reflow accommodates the lack of co-planarity, the surface tension between solder ball and associated pad creates a strong self-centering property to compensate for any placement offsets. However, some problems emerged in practice due to its special features. The major challenges for manufacturer are the inspection of solder joint and to perform touch-up. In most cases, the defect of solder joint cannot be found until in-circuit or functional testing is performed. At this stage, it becomes difficult to determine whether the defect is due to a solder joint or the component itself. Hence controlling the open defect is very important in the PBGA assembling process. It was found that three kinds of defective modes are responsible for the open defect; insufficient heating in the solder melting phase, poor thermal stability of PCB and PBGA and insufficient amount of printing solder paste. Based on the defect mechanism analysis, by optimizing the soldering process, very high assembly yield was achieved.

Solder paste reflow modeling

Solder paste printing and reflow are well established processes for producing solder joints in electronic assemblies. Solder paste consists of a dense suspension of solder particles in a liquid medium (vehicle) that acts as an oxide reducing agent (flux) during reflow, cleaning the metal surfaces of oxides. This paper reports on attempts to model the physical and chemical processes occurring during solder paste reflow using computational fluid dynamics (CRD). Axisymmetric, 2 dimensional and 3‐dimensional models are described, and a method of reproducing oxide‐like behaviour in these models in introduced.

Growth prediction of tin/copper intermetallics formed between 63/37 Sn/Pb and OSP coated copper solder pads for a flip chip application

This study quantifies the effect of temperature and time on the growth of Cu-Sn intermetallics, specifically for flip chip/ball grid array packaging technology. The activation energy and the growth rates were determined for solid state diffusion, after the initial assembly reflow(s). Three different types of solder joints were investigated. 1) BGA 63/37 solder joints which were formed by a standard convection oven attach of 30 mil (760 /spl mu/m)diameter solder spheres to OSP protected, Cu plated ball pads of an organic flip chip substrate. The ball pads are solder mask defined and of 0.635 mm nominal diameter. 2) Flip chip bump pad solder joint consisting of 63/37 eutectic solder bumped die attached to a nonsolder mask defined, OSP protected, Cu plated pad of the flip chip substrate. The flip chip bumps on the die are created by screen printing solder paste on the die pads and subsequent reflow attach, by a standard convection oven to the die under bump metallurgy (UBM). The nominal die UBM pad diameter is 0.085 mm. 3) Solder joint formed on a coupon which involved the reflow of the balls randomly placed on a Cu plated layer with no solder mask coating. The investigation was performed by first establishing the intermetallic growth rate at six different temperatures, ranging from 85/spl deg/C to 150/spl deg/C. The relationship between intermetallic growth and time was shown to essentially follow the common parabolic diffusion relationship to temperature especially above 100/spl deg/C. The activation energy (E/sub a/) and the growth constant (k/sub 0/) were then calculated from this data. The results showed that the E. for the total intermetallic thickness was essentially similar for the three solder joint configurations of the ball, bump and the coupon described above. E. varied from 0.31 eV to 0.32 eV, while the k/sub 0/ varied from 18.0 /spl mu/m/s/sup 1/2 / to 24.2 /spl mu/m/s/sup 1/2 /.

Squeegee bump technology

An innovative solder bumping technology, termed squeegee bumping, has been developed at Motorola's Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to that used for stencil printing. Greater versatility of solder materials can be obtained through solder paste than the electroplating. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118 /spl plusmn/ 3.5 /spl mu/m, and a maximum-to-minimum bump height range of 17 /spl mu/m over a 150 mm-diameter wafer and have been produced repeatedly on test wafers with 210 /spl mu/m peripheral pitch. A 109.6 /spl plusmn/ 1.3 /spl mu/m bump height on orthogonal array with 250 /spl mu/m pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10 /spl times/ reflows and 1008 h of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55/spl deg/C to +125/spl deg/C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 h of autoclave stress at 121/spl deg/C, 100% RH, 15 psig test condition.

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail. This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.

Electroless nickel bumping of aluminum bondpads. I. Surface pretreatment and activation

Electroless nickel bumping of aluminum (Al) bond-pads followed by solder paste printing is seen as one of the lowest cost routes for the bumping of wafers prior to flip-chip assembly. However, the electroless nickel bumping of Al bondpads is not straightforward and a number of activation steps are necessary to enable the nickel deposit to form a strong, electrically conductive bond with the Al. For the electroless nickel coating of mechanical components made of aluminum, a zincate activation process has been used for many years; however, extension of these techniques to semiconductor wafers requires careful control over these pretreatments to avoid damage to the very thin bondpads. This paper reports a number of experiments designed to characterize the activation of Al bondpads to electroless nickel plating, focusing on the effects of solution exposure time and bondpad composition. In addition, the results are discussed in the context of other studies presented in the literature to provide an understanding of the mechanism of the zincate activation process applied to Al bondpads.

다중 슬릿광을 이용한 3차원 Solder Paste 검사 시스템

A 3-dimenstional automatic solder paste inspection system is described that can be used to find defects occurring in solder paste printing process. This system extracts height and volume information very fast as well as area of solder paste printed, using multiple slit ray projection and Galvano-mirror scanning. Methods are presented on calibration of camera and slit projector, real-time image processing of multiple slit images, determination of reference height, and extraction of paste height information are proposed. Performance of the system was successfully demonstrated through field tests.

The definitive guides to solder paste printing

The definitive guides to solder paste printing

Understanding the process window for printing lead-free solder pastes

Solder paste is primarily used as a bonding medium for surface mount assemblies (SMA) in the electronics industry, and is typically deposited using the stencil printing process. Stencil printing is a very important and critical stage in the reflow soldering of surface mount devices, and a high proportion of all SMA defects are related to this process. This is likely to continue with the drive toward the introduction of lead-free solder pastes. Work is continuing on the metallurgical properties of these lead-free solders, including solder joint strength and material compatibility. However, the initial challenge for the new Pb-free formulations is in achieving repeatable solder deposit from print to print and from pad to pad. To meet this challenge, new flux formulations are being developed. For a smooth transition to Pb-free soldering formulations, a proper understanding of the solder paste printing performance is necessary. The key parameters that affect solder paste printing have been identified and are the subject of numerous studies. In lead-free solder paste, the replacement of lead with other elements (including Bi, Cu) changes the density of this dense suspension. In this paper, we investigate the effects of printer parameters, i.e. squeegee speed and pressure (defined as the process window) on the printing performance of a variety of lead-free solder pastes. A three-level design of experiment on these factors was used. Comparisons are presented with lead-rich solder pastes. The metal content of the lead-free solders had a significant effect on the process window.

High precision solder droplet printing technology and the state-of-the-art

The continuing drive toward more complex integrated circuits (ICs) devices having lower cost, higher inputs/outputs (I/Os), greater operating speeds, increased functions per chip, and smaller device geometry has pushed the package requirements far beyond the capability of traditional packages, such as solder paste printing (SPP). Solder droplet printing technology is low cost, non-contact, flexible and data driven, and environmentally friendly has thus been discussed as an enabling technology for precisely placing fine solder deposits onto a variety of smaller substrates. It is therefore suitable for a variety of applications including direct chip attach site preparation, three-dimensional substrates, fine line interconnect, substrate via fill, optoelectronics and many others. It would also allow manufacturing techniques that are impossible or unfeasible with current technology, such as localized replacement of solder on board, depositing solder in different thickness on the same board, or using more than one type of solder on the same board. Recently, many experiments and studies have been under investigation by several groups. In this paper, the principle of the solder droplet printing technology is introduced and recent experimental results and potential application of the technology in the microelectronics industry are also included and evaluated.

Critical factors affecting paste flow during the stencil printing of solder paste

The paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on the printing performance. As the current product miniaturisation trend continues, area array type package solutions are now being designed into products. The assembly of these devices requires the printing of very small solder paste deposits. The printing of solder pastes through small stencil apertures typically results in stencil clogging and incomplete transfer of paste to the PCB pads. At the very narrow aperture sizes required for flip‐chip applications, the paste rheology becomes crucial for consistent paste withdrawal. This is because, for smaller paste volumes, surface tension effects become dominant over viscous flow. Proper understanding of the effect of the key material, equipment and process parameters, and their interactions, is crucial for achieving high print yields. During the aperture filling and emptying sub‐process, the solder paste experiences forces/stresses as it interacts with the stencil aperture walls and the pad surfaces, which directly impact the paste flow within the apertures. As the substrate and stencil separate, the frictional/adhesive force on the stencil walls competes directly with the adhesives/pull force on the PCB pads, often resulting in incomplete paste transfer or skipping/clogged apertures. In this paper, we investigate the effect of stencil design on the printing process and in particular the effect on paste transfer efficiency.

A study of solder paste printing requirements for CSP technology

This paper describes the methodology used to evaluate several different stencil fabrication methods, aperture sizes and thicknesses and different solder pastes. Data collected included the number of printing defects and measurement of solder paste volume and height. Statistics have been used for the analysis of quantitative data. Results from this evaluation have been critical in the success of a new process for CSP assembly in a standard SMT environment. Stencil designs and solder paste selection for other applications have also benefited from the conclusions of this study.

Stencil design for mixed technology through‐hole/SMT placement and reflow

Reviews stencil design requirements for printing solder paste around and in through‐hole pads/openings. There is much interest in this procedure since full implementation allows the placement of both through‐hole components as well as surface mount devices and the subsequent reflow of both simultaneously. This in turn eliminates the need to wave solder or hand solder through‐hole components. The effect of component material type, pin type, lead length, and standoff height of the through hole components is reviewed. Board design issues including plated through‐hole size, pad size, board thickness, and solder mask type are also reviewed. Three stencil designs are considered: single thickness stencils with oversized stencil apertures for overprinting solder paste in the through‐hole pad areas; step stencils with oversized stencil apertures for overprinting solder paste in the through‐hole pad areas; thick stencils (0.384‐0.635 mm thick) for printing solder paste in the through‐hole pad areas. The latter thick stencil is the second stencil in the two‐print stencil process. Several examples are reviewed with the recommended stencil designs.