Solder Joint Crack Research Articles

Transient thermal analysis for accelerated reliability testing of LEDs

Reliability of LED light sources is essential for many general and automotive lighting application where exchange of LED modules would be expensive. Reliability testing to predict the life-time of the devices is required. In this paper transient thermal testing is applied and further developed to monitor the structural integrity of the LED modules during accelerated stress testing. The temperature shock test is one important test because thermo-mechanical stress is a dominating root cause for structural failures as delamination in the package or cracking of solder joints between package and board. New flip chip LEDs (WLP-LEDs) are assembled directly on printed circuit boards (PCB). The initial assembly quality is tested using X-Ray, optical inspection and transient thermal analysis (TTA). In combination the methods deliver essential data to ensure initial assembly quality. Afterwards, the LED modules are exposed to temperature shock tests (−40°C to 125°C) and the TTA is performed repeatedly. By TTA the structural integrity is resolved and cracks or delamination can be identified. Failure modes can be separated and the root cause is investigated by support of transient finite element analysis. One test board is measured In-situ during temperature shock testing. Due to differences in thermo-mechanical stress under hot and cold conditions additional information can be obtained.

Analysis of the BGA solder Sn–3.0Ag–0.5Cu crack interface and a prediction of the fatigue life under tensile stress

In this work, the phenomena of solder joint fatigue fractures are researched. Both shear stress caused by thermal expansion and tensile stress caused by warpage can be the main factor that leads to the fatigue fracture of a solder joint. The fatigue fracture of BGA solder joints under tensile stress is discussed. Experiments were performed to illustrate the position of the BGA solder joint crack interface caused by tensile stress. The fracture interface will appear not only on the solder/Cu pad interface but also on the solder and Cu pad. Moreover, tensile stress and the fatigue life of BGA solder joints caused by warpage are simulated. Then, some significant conclusions are drawn by comparing the experimental results and simulation results. The experimental method can also be used for the other package types in the microelectronics industry.

Analysis of solder joint reliability of high power LEDs by transient thermal testing and transient finite element simulations

An innovative sensitive test method is developed to detect solder joint cracking for high power LED packages. The method is based on transient thermal analysis and can fully replace the still dominating light-on test. For experimental application of the model, test groups of LED packages were soldered with two different lead free solders (SnAgCu305 and Innolot FL-640) on Aluminum Insulated Metal Substrate (Al-IMS) and exposed to temperature cycles. Transient thermal measurements were performed directly after assembly and after specific cycle numbers. After data processing the increase of the relative thermal resistance between the initial signal at “0” cycles and “n” cycles is obtained and correlated with cracks in the solder joint by cross sections. Based on the CAD and material data of the LED package a finite element (FE) model is set up. The time-resolved temperature curves are properly reproduced by transient thermal simulation. The measured “0” cycle curves are fitted using the FE model by adjusting a few material parameters within their allowed tolerance range. A parameter sensitivity analysis is performed. The impact of a crack in the solder joint between package and printed circuit board (PCB) on the time resolved temperature curve is simulated. The simulated crack propagates from the corner of the package to its center. The experimental measured curves are reproduced. Based on the simulation a failure criteria is defined, representing a crack length between 20% and 30% of the solder joint area, and Weibull curves are calculated. A higher creep resistance for the test group soldered with Innolot FL-640 compared to the test group soldered with SAC305 is observed.

Influence of thermal cycling on reliability of solder joints executed on long and metal core PCBs

Purpose – The purpose of this paper is to evaluate the reliability of solder joints made on long FR-4 and metal core printed circuit boards using the accelerated thermal cycling. Design/methodology/approach – Solder joints of diodes and resistors samples made on long FR-4 and aluminum (Al) core printed circuit boards were examined. Two kinds of solder pastes were used for the samples preparation. All samples were subjected to temperature aging cycles (−40°C – 3 hours/+85°C – 3 hours). Solder joints resistance, X-Ray inspection and metallographic cross-sections for samples as received and after 100, 500 and 1,000 hours of thermal cycles were utilized for solder joints assessment. Findings – It was stated that 1,000 hours of thermal cycles were enough to show reliability problems in solder joints on long and/or AL core printed circuit board assembly (PCBA). The solder joints of R1206 components were the most sensitive reliability elements. The solder joints of LED diodes are more reliable than solder joints of R1206 resistors. Solder joints made on FR-4 substrate were about two times more reliable than ones on AL core substrate. Cracks in solder joints were the visible reason of solder joints failures. Originality/value – The influence of thermal cycles on the reliability of solder joints on long, FR-4 and metal core printed circuit boards were presented. Findings from this paper can be used for planning of reliability trials during validation of reflow processes of products containing long or long metal core printed circuit boards (PCBs).

UCPD Model for Pb-Free Solder

A unified creep plasticity damage (UCPD) model for eutectic Sn-Pb and Pb-free solders was developed and implemented into finite element analysis codes. The new model will be described along with the relationship between the model's damage evolution equation and an empirical Coffin–Manson relationship for solder fatigue. Next, developments needed to model crack initiation and growth in solder joints will be described. Finally, experimentally observed cracks in typical solder joints subjected to thermal mechanical fatigue are compared with model predictions. Finite element based modeling is particularly suited for predicting solder joint fatigue of advanced electronics packaging, e.g. package-on-package (PoP), because it allows for evaluation of a variety of package materials and geometries.

Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.

High resolution 3D imaging of bump-bonds by means of synchrotron radiation computed laminography

During the flip-chip bonding process of a semiconductor sensor onto readout electronics, a formation of defects may take place, like solder joint displacements, voids, cracks, pores and bridges. This may result in blind spots on the detector, which are insensitive to photons and thus reduce the detector performance. In this work, the flip-chip interconnections of selected CdTe and GaAs Medipix detectors were investigated by synchrotron radiation computed laminography at a micrometer scale. The analysis of the volume rendering proved the presence of voids in the CdTe sensor flip-chip interconnections, with sizes between 3 μm and 9 μm. These voids can be harmful for the long term use of the device, because their presence weakens the adhesive strength between a contact and the readout electronics. Consequently, their formation needs to be avoided. The GaAs Medipix detectors investigated include two sensors that were produced with different flip-chip methods. The comparison of the 3D renderings of the bump-bond interconnections in the two GaAs sensors demonstrated the presence of a misalignment in the range of 5–12 μm between pixel passivation and bump-bonds in the detector produced with an older technique. In contrast to this, no misalignment was observed for the most recently produced detector. The only remarkable observation is the presence of ``satellites'' of solder that do not compromise the detector operation.

Simulation Investigations on Fluid/Structure Interaction in the Reflow Soldering Process of Board-Level BGA Packaging

The objective of the present study is to develop a Fluid/Structure Interaction model of a board-level Ball Grid Array (BGA) assembly for an infrared-convection reflow oven. The infrared-convection reflow oven is modeled in Computational Fluid Dynamic (CFD) software while the structural heating BGA package simulation is done using Finite Element Method (FEM) software. Both software applications are coupled bidirectional using the Multi-physics Code Coupling Interface (MpCCI). The simulation thermal profile is compared with the experiment thermal profile, and they were found to be in good conformity. The simulated flow fields show that the convection mode in an infrared-convection reflow oven played minor effect on heat transfer to the printed circuit board (PCB). The dominant heat transfer mode in an infrared-convection reflow oven is the radiation mode from a quartz heating tube. From the simulation results, the PCB near the edges or corners tended to heat up first at preheating, soaking and reflow stages. The PCB and component experience larges temperature difference in preheating stage. This situation runs the risk of an excessive board warpage. In addition, the maximum von-Mises stress is trapped in the interfaces between solder joint and die, which intend to form the nucleation of initial solder joint crack. This guideline is very useful for the accurate control of temperature and thermal stress distributions within components and PCB, which is one of major requirements to achieve high reliability of electronic assemblies.

Solder-Joint Quantitative Crack Analysis—Ohmic Resistance Approach

This paper presents a novel technique in the area of solder-joint reliability testing, suggesting a new approach for efficient testing of new products. An analytical model was developed relating the solder-joint ohmic resistance and the joint crack's length caused by temperature cycles. Based on the analytical model, a technique was developed allowing the measurement of a solder-joint's crack length in a nondestructive, continuous way. Thus, prediction of the solder-joint's end-of-life could be done at an early stage of the test, which substantially reduces the test time. This technique of resistance monitoring was validated with a commonly used test vehicle utilizing commercially off-the-shelf daisy-chain quad flat no-lead (QFN44) package. This method is not limited to lab tests, but rather is applicable also for prognostics and preventive maintenance in deployed products.

Nondestructive Sensing of Interconnect Failure Mechanisms Using Time-Domain Reflectometry

This paper presents time-domain reflectometry (TDR) as a nondestructive sensing method for interconnect failure mechanisms. Two competing interconnect failure mechanisms of electronics were considered: solder joint cracking and solder pad cratering. A simple theoretical analysis is presented to explain the effect of each failure mechanism on the TDR reflection coefficient. Mechanical fatigue tests have been conducted to confirm the theoretical analysis. The test results consistently demonstrated that the TDR reflection coefficient gradually decreased as the solder pad separated from the circuit board, whereas it increased during solder joint cracking. Traditional test methods based on electrical resistance monitoring cannot distinguish between failure mechanisms and do not detect degradation until an open circuit has been created. In contrast, the TDR reflection coefficient can be used as a sensing method for the determination of interconnect failure mechanisms as well as for early detection of the degradation associated with those mechanisms.

A Study of Crack Propagation in Pb-Free Solder Joints

The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impact. In order to be able to optimize the drop test performance, it is necessary to have better insight into the crack propagation in the Pb-free solder joints. This study combines crack-front mapping using the dye and pry method and electrical FE simulation to establish a relation between DC electrical resistance and cracked area, and hence monitor the initiation and propagation of cracks in individual solder joints as the PCB assemblies are subjected to JEDEC type mechanical shock and high speed cyclic bending. The carrier in the study is a ball grid array (BGA), a critical component family for drop impact. Combinations of solder alloys and pad finishes, SnPb on organic solderable preservative (OSP), SAC305 on electroless nickel/immersion gold (ENIG), SAC101 on OSP, and SAC101(d) on ENIG are studied regarding the failure mode and crack propagation. This paper demonstrates that, for the large majority of Pb-free solder joints, there is a negligible initiation period; cracks can start forming at the first PCB bending cycle. The presence of large cracks, especially at both sides can increase the compliance of the joint and slow down crack growth. Even if large cracks are present, the resistance increase is less than 1 m¿ per interconnect, which is far from the 100 ¿ that is often taken as a failure criterion. Brittle joints as found with SAC305 on ENIG have erratic propagation rates while ductile joints are much more predictable. Therefore, the way to optimize the drop test performance of a Pb-free BGA assembly is to prolong the crack propagation within the ductile bulk solder material.

Early Detection of Interconnect Degradation by Continuous Monitoring of RF Impedance

Traditional methods used to monitor interconnect reliability are based on measurement of dc resistance. DC resistance is well suited for characterizing electrical continuity, such as identifying an open circuit, but is not useful for detecting a partially degraded interconnect. Degradation of interconnects, such as cracking of solder joints due to fatigue or shock loading, usually initiates at an exterior surface and propagates toward the interior. At frequencies above several hundred megahertz, signal propagation is concentrated at the surface of interconnects, a phenomenon known as the skin effect. Due to the skin effect, RF impedance monitoring offers a more sensitive and reproducible means of sensing interconnect degradation than dc resistance. Since the operation of many types of electronic product requires transmission of signals with significant frequency components in the gigahertz range, this has the further implication that even a small crack at the surface of an interconnect may adversely affect the performance of current and future electronics. This paper demonstrates the value of RF impedance measurements as an early indicator of physical degradation of solder joints as compared to dc-resistance measurements. Mechanical fatigue tests have been conducted with an impedance-controlled circuit board on which a surface mount component was soldered. Simultaneous measurements were performed of dc resistance and time domain reflection coefficient as a measure of RF impedance while the solder joints were stressed. The RF impedance was observed to increase in response to the early stages of cracking of the solder joint while the dc resistance remained constant. Failure analysis revealed that the RF impedance increase resulted from a physical crack, which initiated at the surface of the solder joint and propagated only partway across the solder joint. A comparison between RF impedance and event detectors was made to compare their respective sensitivities in detecting interconnect degradation. These test results indicate that RF impedance can serve as a nondestructive early indicator of solder joint degradation and as an improved means for assessing reliability of high-speed electronics.

Study of Solidification Cracks in Sn-Ag-Cu Lead-Free Solder Joints

In the present work, solidification cracks in Sn-Ag-Cu solder joints were investigated. Experimental results indicate that solidification cracks existed in significant numbers in the miniature Sn-Ag-Cu solder joints. In order to create solidification cracks in the miniature solder joints during solidification and evaluate the susceptibility of Sn-Ag-Cu alloys to solidification cracking, a copper self-restraint specimen was designed, which can simulate the process of solidification crack formation. The solidification crack susceptibility of the Sn-Ag-Cu solder alloy was evaluated using the total crack length of the solder joint. In addition, the effect of trace amounts of elemental additions on solidification cracking of Sn-Ag-Cu solder joints was studied. It was found that adding trace amounts of Ni or Ce could depress the solidification cracks in Sn-3.0Ag-0.5Cu solder joints. However, P additions aggravated the formation of solidification cracks.

Study of Flip Chip Solder Joint Cracks Under Temperature Cycling Using a Laser Ultrasound Inspection System

The current techniques for nondestructive quality evaluation of bumped solder joint connections in electronics packages are either incapable of detecting solder joint cracks, or unsuitable for inline inspection due to cost and throughput reasons. As an alternative, a novel solder joint inspection system is being developed. The system projects short laser pulses onto specimen surface through optic fibers to induce structural vibration. The induced surface displacements are then measured by a laser Doppler vibrometer. A number of digital signal processing algorithms, such as error ratio and correlation coefficient, were used to analyze the vibration responses and identify defective specimens. This paper presents a systematic study of parameters such as error ratio, correlation coefficient, resonant frequency, electrical resistance, and the extension of solder joint cracks, to quantitatively characterize the relationships among them. These relationships verified that the laser ultrasound inspection system provides a reliable and efficient way to evaluate flip chip solder joint cracks nondestructively.

Reliability of BGA and CSP on Metal-Backed Printed Circuit Boards in Harsh Environments

Increased use of sensors and controls in automotive applications has resulted in significant emphasis on the deployment of electronics directly mounted on the engine and transmission. Increased shock, vibration, and higher temperatures necessitate the fundamental understanding of damage mechanisms, which will be active in these environments. Electronics typical of office benign environments uses FR-4 printed circuit boards (PCBs). Automotive applications typically use high glass-transition temperature laminates such as FR4-06 glass∕epoxy laminate material (Tg=164.9°C). In application environments, metal backing of printed circuit boards is being targeted for thermal dissipation, mechanical stability, and interconnections reliability. In this study, the effect of metal-backed boards on the interconnect reliability has been evaluated. Previous studies on electronic reliability for automotive environments have addressed the damage mechanics of solder joints in plastic ball-grid arrays on non-metal-backed substrates (Lall et al., 2003, “Model for BGA and CSP in Automotive Underhood Environments,” Electronic Components and Technology Conference, New Orleans, LA, May 27–30, pp. 189–196;Syed, A. R., 1996, “Thermal Fatigue Reliability Enhancement of Plastic Ball Grid Array (PBGA) Packages,” Proceedings of the 1996 Electronic Components and Technology Conference, Orlando, FL, May 28–31, pp. 1211–1216;Evans et al., 1997, “PBGA Reliability for Under-the-Hood Automotive Applications,” Proceedings of InterPACK ’97, Kohala, HI, Jun. 15–19, pp. 215–219;Mawer et al., 1999, “Board-Level Characterization of 1.0 and 1.27mm Pitch PBGA for Automotive Under-Hood Applications,” Proceedings of the 1999 Electronic Components and Technology Conference, San Diego, CA, Jun. 1–4, pp. 118–124) and ceramic ball-grid arrays (BGAs) on non-metal-backed substrates (Darveaux, R., and Banerji, K., 1992, “Constitutive Relations for Tin-Based Solder Joints,” IEEE Trans-CPMT-A, Vol. 15, No. 6, pp. 1013–1024;Darveaux et al., 1995, “Reliability of Plastic Ball Grid Array Assembly,” Ball Grid Array Technology, Lau, J., ed., McGraw-Hill, New York, pp. 379–442;Darveaux, R., 2000, “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation,” Proceedings of 50th ECTC, May, pp. 1048–1058). Delamination of PCBs from metal backing has also been investigated. The test vehicle is a metal-backed FR4-06 laminate. The printed circuit board has an aluminum metal backing, attached with pressure sensitive adhesive (PSA). Component architectures tested include plastic ball-grid array devices, C2BGA devices, QFN, and discrete resistors. Reliability of the component architectures has been evaluated for HASL. Crack propagation and intermetallic thickness data have been acquired as a function of cycle count. Reliability data have been acquired on all these architectures. Material constitutive behavior of PSA has been measured using uniaxial test samples. The measured constitutive behavior has been incorporated into nonlinear finite element simulations. Predictive models have been developed for the dominant failure mechanisms for all the component architectures tested.

Dynamic responses and solder joint reliability under board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, the comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to the solder joint failure mechanism. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layer, are studied by comparing and analyzing the dynamic responses. A good repeatability of testing can only be achieved when careful attentions are paid on these factors. The relationships among drop height, peak acceleration, pulse duration, and impact energy are unique for a drop tester, and therefore, it should be characterized prior to the reliability tests. The studies also help to determine the requirements of new impact pulse quickly. The bending mode shapes and frequencies of PCB are extracted from dynamic strains and images token by high-speed camera. A real-time dynamic resistance monitoring method is developed to study the solder joint reliability. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint crack failure. Cyclic changes of dynamic resistance indicate that the solder joint crack opens and closes when PCB bends up and down.

Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests

Detection of flip chip solder joint cracks using correlation coefficient and auto-comparison analyses of laser ultrasound signals

The detection of cracks in solder joints has been a challenge for the current nondestructive inspection techniques. This paper investigates the capability of a laser ultrasound and vibrometer inspection system to detect thermal cycle induced cracks in flip chip solder joints. Correlation coefficient analysis of ultrasound vibration signals is presented and compared with the previous error ratio method. The correlation coefficient method improves the system's signal-to-noise ratio. Optimum detection locations on the chip surface are investigated and an auto-comparison method is introduced to inspect a chip with fewer detection points and without the dependence on a reference chip. The results show that the system is able to identify thermally cracked solder joints from well-connected joints. When fully developed, the system can be put in-line and serve as a low-cost go/no-go inspection tool to screen out defects in solder joints at an early stage in the manufacturing process. It can also be used to evaluate the quality of many other types of electronic packages and other devices.

Solder joint reliability in AgPt‐metallized LTCC modules

PurposeTo investigate the effect of the metallization and solder mask materials on the solder joint reliability of low temperature co‐fired ceramic (LTCC) modules.Design/methodology/approachThe fatigue performance of six LTCC/PCB assembly versions was investigated using temperature cycling tests in the −40‐125°C and 20‐80°C temperature ranges. In order to eliminate fatigue cracking in the LTCC module itself, large AgPt‐metallized solder (1 mm) lands with organic or co‐fired glaze solder masks, having 0.86‐0.89 mm openings, were used. The performance of these modules was compared to that of AgPd‐metallized modules with a similar solder land structure. The joint structures were analysed using resistance measurements, scanning acoustic microscopy, SEM/EDS investigation, and FEM simulations.FindingsThe results showed that failure distributions with Weibull shape factor (β) values from 8.4 to 14.2, and characteristic life time (θ) values between 860 and 1,165 cycles were achieved in AgPt assemblies in the −40‐125°C temperature range. The primary failure mechanism was solder joint cracking, whereas the AgPd‐metallized modules suffered from cracking in the ceramic. In the milder test conditions AgPd‐metallized modules showed better fatigue endurance than AgPt‐metallized modules.Originality/valueThis paper proves that the cracking in ceramic in the harsh test condition can be eliminated almost completely by using AgPt metallization instead of AgPd metallization in the present test module structure.

DESIGN FOR BOARD LEVEL RELIABILITY OF A MINIATURIZED MEMS PACKAGE: STACKED DIE TQFN

International Journal of Computational Engineering ScienceVol. 04, No. 02, pp. 347-350 (2003) PackagingNo AccessDESIGN FOR BOARD LEVEL RELIABILITY OF A MINIATURIZED MEMS PACKAGE: STACKED DIE TQFNTONG Y. TEE, GIOVANNI FREZZA, MAYHUAN LIM, HUN S. NG, FEDERICO ZIGLIOLI, and ZHAOWEI ZHONGTONG Y. TEESTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , GIOVANNI FREZZASTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , MAYHUAN LIMSTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , HUN S. NGSTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , FEDERICO ZIGLIOLISTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , and ZHAOWEI ZHONGNanyang Technological University, School of MPE, 50 Nanyang Ave, Singapore 639798, Singapore Search for more papers by this author https://doi.org/10.1142/S1465876303001241Cited by:4 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractA new type of MEMS 3D package is introduced: stacked die Thick Quad Flat Non-lead (TQFN), for application as a multiple axis linear accelerometer. Both solder joint and die reliability during board level thermal cycling test are important concerns, as they affect the functionality and quality of the product. Design analyses are performed to study the effects of 12 key design variations in package dimensions and material properties, on solder joint reliability.Keywords:QFNStacked DieAccelerometerSolder Joint Reliability References R. Darveaux, Effect of Simulation Methodology on Solder Joint Crack Growth Correlation, Proc. 50th ECTC Conference, Las Vegas, NE (2000) 1048-1058 . Google Scholar T. Y. Tee, H. S. Ng, J. Diot, G. Frezza, R. Tiziani and G. Santospirito, Comprehensive Design Analysis of QFN and PowerQFN Packages for Enhanced Board Level Solder Joint Reliability, Proc. 52nd ECTC Conference, San Diego, CA (2002) 985-991 . Google Scholar T. Y. Tee, M. Lim, H. S. Ng, X. Baraton, D. Kaire and Z. W. Zhong, Design Analysis of Solder Joint Reliability for Stacked Die Mixed Flip-Chip and Wirebond BGA, Proc. 4th EPTC Conference, Singapore (2002) 391-397 . Google ScholarW. W. Lee, L. T. Nguyen and G. S. Selvaduray, Microelectronics Reliability 40, 231 (2000). Crossref, Google Scholar FiguresReferencesRelatedDetailsCited By 4Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packagesTong Yan Tee and Zhaowei Zhong1 Dec 2004 | Microelectronics Reliability, Vol. 44, No. 12Absolute and relative fatigue life prediction methodology for virtual qualification and design enhancement of lead-free BGA Hun Shen Ng, Tong Yan Tee, Kim Yong Goh, Jing-en Luan and T. Reinikainen et al.Design analysis of touch chip for enhanced package and board level reliability Tong Yan Tee, Hun Shen Ng, H. Siegel, R. Bond and Zhaowei Zhong4-Dimensional Design Analysis and Optimization of System-in-Package Tong Yan Tee, Hun Shen Ng, Jing-en Luan, Xueren Zhang and Kim Yong Goh et al. Recommended Vol. 04, No. 02 Metrics History KeywordsQFNStacked DieAccelerometerSolder Joint ReliabilityPDF download