Solder Joint Configurations Research Articles

Eddy current soldering of solar cell ribbons under a layer of glass

Thermal fatigue of soldered interconnections of silicon solar cells is considered one of the key failure modes in photovoltaic (PV) modules. Due to differences in thermal expansion coefficients of the used materials, cracks and disconnected wiring can occur, causing a local increase of resistance. This can lead to hot spots and early failure of a panel. In this research, we develop eddy current soldering as a non-contact soldering technique for tabbing the ribbon of PV cells under a layer of glass. The performance of eddy current soldering was studied in detail by changing an induction coil distance to the treated sample from 2 to 4 mm and varying exposure time. An IR camera monitored temperature profiles at the soldering zone, and I–V curves of samples were extracted to validate the soldering technique and the efficiency of the tabbing process. Electroluminescence imaging was deployed to monitor cracking after the soldering process; scanning electron microscopy (SEM) and scanning acoustic microscopy (SAM) were used to investigate the microstructure and cracking within the solder joint and silicon. The results showed that the shortest exposure times at a 2 mm heating distance caused higher risks for cracks in silicon. The intermediate exposures at a 3 mm heating distance increased the likelihood of cracking in the solder joint. For the longest heating times at a distance of 4 mm, the solder joint appeared crack free, although, in some areas, poor wetting of solder was observed. The performance of eddy current soldering under a layer of glass was compared to manually soldered samples. Based on the I–V curves, all samples were functional, and differences between exposure times and manually soldered samples were not evident. Thus, only electrical verification of the solder quality was insufficient. Due to the study, it was concluded that the proper solder interconnections through glass could be made by using the eddy current soldering process and a sufficient exposure time to avoid cracking within the solder joint configuration and silicon.

Effect of ENIG deposition on the failure mechanisms of thermomechanically loaded lead‐free 2nd level interconnections in LTCC/PWB assemblies

PurposeThe purpose of this paper is to investigate the effect of electroless NiAu (ENIG) deposition on the failure mechanisms and characteristic lifetimes of three different non‐collapsible lead‐free 2nd level interconnections in low‐temperature co‐fired ceramic (LTCC)/printed wiring board (PWB) assemblies.Design/methodology/approachFive LTCC module/PWB assemblies were fabricated and exposed to a temperature cycling test over a −40 to 125°C temperature range. The characteristic lifetimes of these assemblies were determined using direct current resistance measurements. The failure mechanisms of the test assemblies were verified using X‐ray and scanning acoustic microscopy, optical microscopy with polarized light, scanning electron microscope (SEM)/energy dispersive spectroscopy and field emission‐SEM investigation.FindingsA stable intermetallic compound (IMC) layer is formed between the Ni deposit and solder matrix during reflow soldering. The layer thickness does not grow excessively and the interface between the layer and solder is practically free from Kirkendall voids after the thermal cycling test (TCT) over a temperature range of −40 to 125°C. The adhesion between the IMC layer and solder matrix is sufficient to prevent separation of this interface, resulting in intergranular (creep) or mixed transgranular/intergranular (fatigue/creep) failure within the solder matrix. However, the thermal fatigue endurance of the lead‐free solder has a major effect on the characteristic lifetime, not the deposit material of the solder land. Depending on the thickness of the LTCC substrate and the composition of the lead‐free solder alloy, characteristic lifetimes of over 2,000 cycles are achieved in the TCT.Originality/valueThe paper investigates in detail the advantages and disadvantages of ENIG deposition in LTCC/PWB assemblies with a large global thermal mismatch (ΔCTE≥10 ppm/°C), considering the design and manufacturing stages of the solder joint configuration and its performance under harsh accelerated test conditions.

Characterization of Sn7In4.1Ag0.5Cu solder in lead‐free composite solder joints of LTCC/PWB assembly

PurposeThe purpose of this paper is to present a novel Sn7In4.1Ag0.5Cu/Plastic Core Solder Ball/Sn4Ag0.5Cu composite solder joint configuration for second‐level ball grid array (BGA) interconnections of low temperature co‐fired ceramic (LTCC) modules and the thermal fatigue durability of the configuration. The purpose of using the Sn7In4.1Ag0.5Cu solder was to increase the creep/fatigue resistance of critical regions on the LTCC side of the joint.Design/methodology/approachTest LTCC module/printed wiring board (PWB) assemblies were fabricated and exposed into temperature cycling tests over the 0 to 100°C and −40 to 125°C temperature ranges. The characteristic lifetimes of these assemblies were determined using DC resistance measurements. The failure mechanisms of the test assemblies were verified using scanning acoustic microscopy, FE‐SEM, and SEM investigation.FindingsThe test assemblies were exposed to thermal cycling tests (TCT) over test ranges of 0 to 100°C and −40 to 125°C, and characteristic lifetimes of over 5,500 and 1,400 cycles, respectively, were achieved. Compared with Sn4Ag0.5Cu/plastic‐core solder balls (PCSB)/Sn4Ag0.5Cu joints, the characteristic lifetime of the SAC‐In/PCSB/SAC joints increased over 55 per cent in the harsh (−40 to 125°C) TCT conditions. In the milder test conditions (0 to 100°C), the characteristic lifetime of the SAC‐In/PCSB/SAC joints increased 30 per cent compared with the SAC/PCSB/SAC joints.Originality/valueThe results proved that the enhanced creep/fatigue properties of the solder matrix resulted in satisfactory lifetime durations in the present lead‐free composite solder joints and, consequently, different primary failure mechanisms on the LTCC side due to the use of indium alloyed solder. Thus, the present joint configuration is assumed to be a promising solution for the further design of a reliable second‐level solder interconnection in LTCC/PWB assemblies with a high‐global thermal mismatch.

Thermal cycling reliability of lead‐free chip resistor solder joints

The solder joint reliability of ceramic chip resistors assembled to laminate substrates has been a long time concern for systems exposed to harsh environments. In this work, the thermal cycling reliability of several 2512 chip resistor lead‐free solder joint configurations has been investigated. In an initial study, a comparison has been made between the solder joint reliabilities obtained with components fabricated with both tin‐lead and pure tin solder terminations. In the main portion of the reliability testing, two temperature ranges (−40‐125°C and −40‐150°C) and five different solder alloys have been examined. The investigated solders include the normal eutectic Sn‐Ag‐Cu (SAC) alloy recommended by earlier studies (95.5Sn‐3.8Ag‐0.7Cu), and three variations of the lead‐free ternary SAC alloy that include small quaternary additions of bismuth and indium to enhance fatigue resistance.

Interfacial Bond Stress Relationship for Gullwing Solder Joints

Lead frame bond connections are susceptible to bond shear and peeling stress failure due to high thermomechanical loads resulting from the combined effects of thermal and vibration effects. Solder joint integrity has also been found to be highly dependent on the solder joint configuration, which, in turn, is determined by bond pad size, the alloy material, and the lead frame geometric details. This study considers the complete joint configuration in formulating the expression for bond stress. A new bond stress equation is proposed to predict the solder joint peeling stress at the interface between gullwing lead-frame and the solder layer. The proposed method considers the complete solder joint subjected to combined thermomechanical forces. Prior studies utilized symmetry conditions across the joint.

Growth prediction of tin/copper intermetallics formed between 63/37 Sn/Pb and OSP coated copper solder pads for a flip chip application

This study quantifies the effect of temperature and time on the growth of Cu-Sn intermetallics, specifically for flip chip/ball grid array packaging technology. The activation energy and the growth rates were determined for solid state diffusion, after the initial assembly reflow(s). Three different types of solder joints were investigated. 1) BGA 63/37 solder joints which were formed by a standard convection oven attach of 30 mil (760 /spl mu/m)diameter solder spheres to OSP protected, Cu plated ball pads of an organic flip chip substrate. The ball pads are solder mask defined and of 0.635 mm nominal diameter. 2) Flip chip bump pad solder joint consisting of 63/37 eutectic solder bumped die attached to a nonsolder mask defined, OSP protected, Cu plated pad of the flip chip substrate. The flip chip bumps on the die are created by screen printing solder paste on the die pads and subsequent reflow attach, by a standard convection oven to the die under bump metallurgy (UBM). The nominal die UBM pad diameter is 0.085 mm. 3) Solder joint formed on a coupon which involved the reflow of the balls randomly placed on a Cu plated layer with no solder mask coating. The investigation was performed by first establishing the intermetallic growth rate at six different temperatures, ranging from 85/spl deg/C to 150/spl deg/C. The relationship between intermetallic growth and time was shown to essentially follow the common parabolic diffusion relationship to temperature especially above 100/spl deg/C. The activation energy (E/sub a/) and the growth constant (k/sub 0/) were then calculated from this data. The results showed that the E. for the total intermetallic thickness was essentially similar for the three solder joint configurations of the ball, bump and the coupon described above. E. varied from 0.31 eV to 0.32 eV, while the k/sub 0/ varied from 18.0 /spl mu/m/s/sup 1/2 / to 24.2 /spl mu/m/s/sup 1/2 /.

Solder Joint Formation Simulation and Component Tombstoning Prediction During Reflow

The failure of electrical devices associated with solder joints has become one of the most critical reliability issues for surface-mounted devices. Solder joint reliability performance has been found to be highly dependent on the solder joint configuration, which, in turn, is governed by bond pad size, alloy material, and leadframe structure, as well as solder reflow characteristics. To investigate tombstone effects causing solder joint failure during leadless component reflow process, this work has focused on (1) developing a numerical model for the simulations of the solder joint formation during the reflow process, and (2) determining possibility that a tombstone effect for the leadless component may occur by analyzing the force and torque in the problem. Using this methodology, the tombstone effect associated with different pad geometry configurations and solder paste amount has been analyzed through the application of the public domain software tool Surface Evolver. Simulations show that the tombstoning is very sensitive to pad/component geometry design, solder surface tension, solder paste volume, wetting area, and wetting angle. This model simulation can be used to determine optimal solder paste volume, pad geometry configurations, and solder material for avoiding tombstone effects.

THERMAL CYCLING OF TEMPERATURE AND STRAIN RATE DEPENDENT SOLDER JOINTS

In a previous paper, i.e., Skipor et al. (1996), 63/37 Sn/Pb eutectic solder was characterized with the viscoplastic model of Bodner and Partom (1975). The material parameters of the isotropic form of the Bodner–Partom model were found for the eutectic solder as functions of temperature. In the present paper, the resulting temperature dependent viscoplastic description for the eutectic is implemented in an infinitesimal strain incrementally linear finite element method. This finite element method is based on an explicit, second-order accurate time-integration scheme, which is presented herein. The finite element method so-obtained is then used to analyze two solder joint configurations under cyclic thermal loading. The results of the analyses show that, along with observed field performance of solder joints, the details of the plastic strain distribution within a joint, i.e., its magnitude and degree of diffuseness, can have large impact on joint reliability. Specifically, it is demonstrated that the geometric details of how solder in a joint connects to harder materials in an electronic package play a significant role.

A Procedure for Automated Shape and Life Prediction in Flip-Chip and BGA Solder Joints

In this paper, a three-dimensional shape prediction model and a finite element solution procedure for flip-chip and BGA solder joints are developed. The developed system is capable of calculating the solder joint geometry and the fatigue life automatically without any intervention from the user. The automation achieved will enable fast reliability estimation and improved accuracy, since the two-dimensional finite element mesh used for solder shape prediction is used to generate the three-dimensional finite element mesh for stress analysis. The implementation of the procedure is verified using the solution for a flip-chip joint from literature, and the capability of the code is demonstrated on a hypothetical three-dimensional solder joint with square pads that are rotated with respect to each other, and offset from each other. The system developed in the study represents the first instance of an integrated, automated finite element procedure for both shape and fatigue life prediction in general three-dimensional solder joints. The automation achieved in the system enables fast reliability estimation in a design environment, and the optimal design of flip-chip and BGA solder joint configurations for maximum life.

Applying a physics‐of‐failure model to predicting surface mount solder joint reliability

AbstractTo address the wide variety of solder joint configurations, the authors have developed and applied a physics‐of‐failure model to predicting the service life of solder joints under thermal cycling conditions. The wide variety of solder joint geometries, materials and environments makes it impractical to develop and apply empirical models to predicting the service life of solder joint interconnects. On the other hand, a physics‐of‐failure model that describes the failure mechanisms in solder joints can be applied to a wide range of conditions. The physics‐of‐failure model framework is described and a model is demonstrated for predicting the failure of a leadless surface mount solder joint under slow thermal cycling conditions.

Creep-Fatigue Behavior of Microelectronic Solder Joints

ABSTRACTEven at room temperature, solder joints exhibit both creep and fatigue behavior that is strongly dependent on solder joint configuration, the thermal environment, and the solder alloy properties. The microstructures of solder joints with up to 25 years of aging have been studied using SEM/EDS and metallographic techniques. Data are presented on grain growth and metallurgical composition versus aging time. A special non-linear finite element creep-fatigue simulation model has been developed, based on measured strain-rate hardness relationships, and used to analytically predict the effects of observed metallurgical changes and the effects of lead stiffness in solder joint creepfatigue interaction. To corroborate the analytical results, a special bi-metallic test fixture has been developed to accelerate the thermo-mechanical loading of solder joints in thermal cycling environments. Measured time-to-failure data for various electronicpackage lead configurations/stiffnesses, including gullwing and J-lead, are presented and shown to be in reasonable agreement with the analytical results.

Creep-Fatigue Behavior of Microelectronic Solder Joints

AbstractEven at room temperature, solder joints exhibit both creep and fatigue behavior that is strongly dependent on solder joint configuration, the thermal environment, and the solder alloy properties. The microstructures of solder joints with up to 25 years of aging have been studied using SEM/EDS and metallographic techniques. Data are presented on grain growth and metallurgical composition versus aging time. A special non-linear finite element creep-fatigue simulation model has been developed, based on measured strain-rate hardness relationships, and used to analytically predict the effects of observed metallurgical changes and the effects of lead stiffness in solder joint creepfatigue interaction. To corroborate the analytical results, a special bi-metallic test fixture has been developed to accelerate the thermo-mechanical loading of solder joints in thermal cycling environments. Measured time-to-failure data for various electronicpackage lead configurations/stiffnesses, including gullwing and J-lead, are presented and shown to be in reasonable agreement with the analytical results.

Direct Attachment of Leadless Chip Carriers to Organic Matrix Printed Wiring Boards

A test program was performed that compares the reliability of various leadless chip carrier (LCC) solder joint configurations under conditions of temperature cycling from -55 to +125°C. Since there is a coefficient of thermal expansion mismatch between the ceramic body of the LCC (6 ppm/°C) and that of an epoxy-glass printed wiring board (15 ppm/°C), it was of interest to determine the optimum solder joint configuration that results in maximum reliability after extensive exposure to temperature extremes. This configuration was determined to be the one that results in a 45° solder fillet; consequently, the distance the printed wiring board (PWB) pad extends beyond the edge of the LCC is a critical requirement. For an 18 pad LCC, this distance is 40 mils. Information on the use of various substrates for leadless chip carriers is also discussed.