Eddy current soldering of solar cell ribbons under a layer of glass

Abstract

Thermal fatigue of soldered interconnections of silicon solar cells is considered one of the key failure modes in photovoltaic (PV) modules. Due to differences in thermal expansion coefficients of the used materials, cracks and disconnected wiring can occur, causing a local increase of resistance. This can lead to hot spots and early failure of a panel. In this research, we develop eddy current soldering as a non-contact soldering technique for tabbing the ribbon of PV cells under a layer of glass. The performance of eddy current soldering was studied in detail by changing an induction coil distance to the treated sample from 2 to 4 mm and varying exposure time. An IR camera monitored temperature profiles at the soldering zone, and I–V curves of samples were extracted to validate the soldering technique and the efficiency of the tabbing process. Electroluminescence imaging was deployed to monitor cracking after the soldering process; scanning electron microscopy (SEM) and scanning acoustic microscopy (SAM) were used to investigate the microstructure and cracking within the solder joint and silicon. The results showed that the shortest exposure times at a 2 mm heating distance caused higher risks for cracks in silicon. The intermediate exposures at a 3 mm heating distance increased the likelihood of cracking in the solder joint. For the longest heating times at a distance of 4 mm, the solder joint appeared crack free, although, in some areas, poor wetting of solder was observed. The performance of eddy current soldering under a layer of glass was compared to manually soldered samples. Based on the I–V curves, all samples were functional, and differences between exposure times and manually soldered samples were not evident. Thus, only electrical verification of the solder quality was insufficient. Due to the study, it was concluded that the proper solder interconnections through glass could be made by using the eddy current soldering process and a sufficient exposure time to avoid cracking within the solder joint configuration and silicon.