Solder Interconnects Research Articles

Effect of Thermal Aging and Salt Spray Testing on Reliability and Mechanical Strength of Sn–58Bi Lead-Free Solder

Low-cost manufacturing in the electronics industry is becoming more demanding, particularly in the production of consumer electronics. Such manufacturing processes require reliable and low-cost lead-free solders. Among the low-temperature lead-free solders, eutectic Sn-Bi solder attracts a great deal of interest as it offers good reliability compared with that of Sn-Pb solders. In this paper, the reliability of eutectic 42%Sn-58%Bi (wt.%) lead-free solder is studied using combinations of environmental tests such as thermal aging (TA) at 100 °C, salt spray test (SST), and a sequential combination of TA and SST. Microstructural studies on the samples are performed at different time intervals. To study the effect of salt spray and TA on the mechanical reliability, drop testing is performed on the samples. Failure analysis is conducted after different tests. Marked corrosion is seen after the SST. This also has a considerable effect on the impact strength of the solder interconnections. TA increases the thickness of the intermetallic layers, which is found to affect the drop performance.

Influence of High-G Mechanical Shock and Thermal Cycling on Localized Recrystallization in Sn-Ag-Cu Solder Interconnects

The impact of isothermal aging and recrystallized grain structure distribution on mechanical shock and thermal cycling performance of solder joints with 1% and 3% silver content Sn-Ag-Cu interconnects were investigated. Localized recrystallized grain structure distributions were analyzed to identify correlations between the microstructure evolution and shock performance. The results reveal that the shock tolerance depends on the amount of shock energy that can be absorbed during each shock cycle, which depends on microstructural features. Based on the recrystallized grain distribution, additional isothermal aging in 1% silver Sn-Ag-Cu interconnects shows improved shock performance, whereas degraded shock performance was observed in 3% Sn-Ag-Cu interconnects. Using the same grain boundary distribution analysis on thermally cycled samples, relationships between the particle size distribution, localized recrystallized grain structure development, shock, and thermomechanical performance were identified: finer particle spacing is beneficial for thermal cycling as it resists grain boundary generation, while conversely, wider particle spacing facilitates recrystallization and grain boundary mobility that allows Sn to absorb shock energy.

Effect of grain orientation on mechanical properties and thermomechanical response of Sn-based solder interconnects

The thermomechanical response of Sn-based solder interconnects with differently oriented grains was investigated by electron backscattered diffraction technique under thermal cycling and thermal shock testing in this study. The results showed that deformation and cracking of solder interconnects have a close relationship with the unique characteristics of grain orientation and boundaries in each solder interconnect, and deformation was frequently confined within the high-angle grain boundaries. The micro Vickers hardness testing results showed that the hardness varied significantly depending on the grain orientation and structure, and deformation twins can be induced around the indents by the indentation testing.

Effect of surface treatment on the high-speed drop reliability of Pb-free solder interconnect

This study utilized a solder ball shear test to evaluate the mechanical behavior of Sn–3.0Ag–0.5Cu/Cu and Sn–3.0Ag–0.5Cu/electroless Ni-immersion Au solder joints under high speed loading and hence the drop reliability. The combination of the force–displacement graphs captured from the shear tests and the fracture morphology analysis discloses three fracture modes active in our samples, which include a ductile fracture occurring through the solder (Mode I), a brittle fracture along the interface with intermetallic compound (IMC) layer after some plastic deformation in the solder (Mode II), and a brittle fracture through the IMC layer with almost no plastic deformation (Mode III). Identifying a fracture mode dominant in the samples for different solder joints and shear speeds leads us to conclude that the drop reliability of solder joints is highly related to the morphology of the IMC formed at the interface and the strain rate applied to the joints. These results underscore the utility of the experimental methodology adopted in this study to evaluate the drop reliability of solder joints.

Modeling the Rate-Dependent Durability of Reduced-Ag SAC Interconnects for Area Array Packages Under Torsion Loads

Solder durability models frequently focus on the applied strain range; however, the rate of applied loading, or strain rate, is also important. In this study, an approach to incorporate strain rate dependency into durability estimation for solder interconnects is examined. Failure data were collected for SAC105 solder ball grid arrays assembled with SAC305 solder that were subjected to displacement-controlled torsion loads. Strain-rate-dependent (Johnson–Cook model) and strain-rate-independent elastic–plastic properties were used to model the solders in finite-element simulation. Test data were then used to extract damage model constants for the reduced-Ag SAC solder. A generalized Coffin–Manson damage model was used to estimate the durability. The mechanical fatigue durability curve for reduced-silver SAC solder was generated and compared with durability curves for SAC305 and Sn-Pb from the literature.

Thermal Cycling Reliability of Sn-Ag-Cu Solder Interconnections. Part 1: Effects of Test Parameters

The work presented in part 1 of this study focuses on identifying the effects of thermal cycling test parameters on the lifetime of ball grid array (BGA) component boards. Detailed understanding about the effects of the thermal cycling parameters is essential because it provides means to develop more efficient and meaningful methods of reliability assessment for electronic products. The study was carried out with a single package type (BGA with 144 solder balls), printed wiring board (eight-layer build-up FR4 structure), and solder interconnection composition (Sn-3.1Ag-0.5Cu) to ensure that individual test results would be comparable with each other. The effects of (i) temperature difference (ΔT), (ii) lower dwell temperature and lower dwell time, (iii) mean temperature, (iv) dwell time, and (v) ramp rate were evaluated. Based on the characteristic lifetimes, the thermal cycling profiles were categorized into three lifetime groups: (i) highly accelerated conditions, (ii) moderately accelerated conditions, and (iii) mildly/nonaccelerated conditions. Thus, one might be tempted to use the highly accelerated conditions to produce lifetime statistics as quickly as possible. However, to do this one needs to know that the failure mechanisms do not change from one lifetime group to another and that the failure mechanisms correlate with real-use failures. Therefore, in part 2 the observed differences in component board lifetimes will be explained by studying the failure mechanisms that take place in the three lifetime groups.

The Effects of Concurrent Power and Vibration Loads on the Reliability of Board-Level Interconnections in Power Electronic Assemblies

The effect of concurrent vibration and electrical power loads on the solder interconnections of a surface-mount power transistor package has been investigated in this work. Both cyclic and constant power loadings were separately combined with vibration over a wide amplitude range. Single load vibration and power cycling tests were conducted for comparison. In addition to lifetime analysis, the failure modes occurring under each test case were carefully studied from cross-sectional samples, and the failure mechanisms were rationalized with the help of finite-element calculations and microstructural analysis. A substantial reduction in interconnection lifetimes was observed in the combined load tests as compared with the lifetime under single load tests. Three different failure modes were found within all the different test cases: 1) ductile crack propagation through bulk solder, 2) recrystallization assisted crack propagation, and 3) mixed mode propagation with both mechanisms. The failure mode changes were dependent mainly on the magnitude of plastic strain induced by the mechanical vibration. The results of this study provide insight in designing more comprehensive reliability tests as well as achieving higher levels of test acceleration without compromising the validity of results.

Thermal Cycling Reliability of Sn-Ag-Cu Solder Interconnections—Part 2: Failure Mechanisms

Part 1 of this study focused on identifying the effects of (i) temperature difference (ΔT), (ii) lower dwell temperature and shorter dwell time, (iii) mean temperature, (iv) dwell time, and (v) ramp rate on the lifetime of ball grid array (with 144 solder balls) component boards. Based on the characteristic lifetime, the studied thermal cycling profiles were categorized into three groups: (i) highly accelerated conditions, (ii) moderately accelerated conditions, and (iii) mildly/nonaccelerated conditions. In this work, the observed differences in component board lifetime are explained by studying the failure mechanisms and microstructural changes that take place in the three groups of loading conditions. It was observed that, under the standardized thermal cycling conditions (highly accelerated conditions), the networks of grain boundaries formed by recrystallization provided favorable paths for cracks to propagate intergranularly. It is noteworthy that the coarsening of intermetallic particles was strong in the recrystallized regions (the cellular structure had disappeared completely in the crack region). However, under real-use conditions (mildly/nonaccelerated conditions), recrystallization was not observed in the solder interconnections and cracks had propagated transgranularly in the bulk solder or between the intermetallic compound (IMC) layer and the bulk solder. The real-use conditions showed slight coarsening of the microstructure close to the crack region, but the solder bulk still included finer IMC particles and β-Sn cells characteristic of the as-solidified microstructures. These findings suggest that standardized thermal cycling tests used to assess the solder interconnection reliability of BGA144 component boards create failure mechanisms that differ from those seen in conditions representing real-use operation.

Solidification and reliability of lead‐free solder interconnection

PurposeAs a literature review article, the purpose of this paper is to highlight the intricate interaction and correlation between the interconnection microstructure and the failure mechanism. It is therefore critical to summarize all the challenges in understanding solder solidification of interconnections.Design/methodology/approachLiterature review.FindingsSolidification of solder interconnections is therefore critical because it is the process during which the solder interconnection is formed. The as‐solidified microstructure serves as the starting point for all failure modes. Because of the miniaturization of electronics, the interconnection size decreases continuously, already to such a range that solder solidification takes place remarkably differently from the bulk ingot, on which solidification studies have been focused for decades. There are many challenges in understanding the solidification of tiny solder interconnections, including the complex metallurgical system, dynamic solder composition, supercooling and actual solidification temperature, localized temperature field, diverse interfacial IMC formation, and so on, warranting further research investment on solder solidification.Originality/valueThis paper provides a critical overview of the concerns in solidification study for lead‐free solder interconnection. It is probably an article initiating more attention towards solidification topics.

Finite element analysis of thermal distributions of solder ball in flip chip ball grid array using ABAQUS

PurposeThe increased use recently of area‐array technology in electronic packaging has similarly increased the importance of predicting the thermal distribution of area‐array solder interconnection. As the interconnection technology for flip chip package is getting finer and smaller, it is extremely difficult to obtain the accurate values of thermal stresses by direct experimental measurements. Different types of solder bumps used for interconnection would also influence the thermal distribution within the package. Because the solder balls are too small for direct measurement of their stresses, finite element method (FEM) was used for obtaining the stresses instead.Design/methodology/approachThis paper will discuss the results of the thermal stress distribution using numerical method via ABAQUS software. The variation of the thermal stress distribution with the temperature gradient model was evaluated to study the effects of the different material thermal conductivity of solder bumps used. A detailed 2D finite element model was constructed to perform 2D plain strain elastoplastic analysis to predict areas of high stress.FindingsIt is found that thermal distribution of solder bumps starts to propagate from the top region to the bottom region of the solder balls. Other than that, thermal stress effect increases in parallel with the increasing of the temperature. The simulation results shows that leaded solder balls, SnPb have higher maximum thermal stress level compared to lead‐free SAC solder balls.Originality/valueThe paper describes combination of stress with thermal loading correlation on a flip chip model. The work also shows how the different thermal conductivity on solder balls influences the thermal induced stress on the flip chip package.

Cohesive fracture mechanics based numerical analysis to BGA packaging and lead free solders under drop impact

Lead free solders are replacing lead rich solders in the electronic industry, the performance and safety of lead free solder interconnects in electric packaging under drop impact becomes a critical concern of semiconductor and electronic product manufacturers. Compared with the lead rich solder alloy, lead free solder alloy typically has higher rigidity and lower ductility. The presence of the Intermetallic Compound (IMC) layer can also affect the drop impact response of the solder interconnect, which may lead to quasi-brittle solder/IMC interfacial fracture. The traditional drop test is expensive and time consuming, and it is quite difficult to observe the full dynamic responses during the drop impact. In the present study, numerical analysis is performed to investigate drop impact effect on ball grid array (BGA) electronic packaging with the intention of predicting the performance of solders under drop impact and providing the fundamental understanding required to design a reliable electric packaging. A three dimensional finite element model is developed to simulate the solder interconnect and electronic packaging failure under board-level drop impact. An impact analysis procedure coupled with sub-modeling technique is established. The Cu6Sn5 and Cu3Sn IMC layers are incorporated in the solder interconnects model; cohesive fracture mechanics based method is applied to predict the crack initiation and propagation near the IMC/solder interface. A lead-free solder alloy constitutive relationship comprising elastic and rate dependent plastic effects is incorporated in the computational model.

Effect of ENEPIG Surface Finish on the Vibration Reliability of Solder Interconnects

Surface finishes are used to preserve and promote solderability of exposed copper metallization on printed wiring boards. While in the best of worlds, the solder used in assembly should dictate the solder interconnect reliability, surface finishes are known to have an effect. The effect of surface finishes on solder interconnect reliability can be particularly strong under high strain rate loading conditions. In this study, durability of solder interconnects formed between BGAs and electroless nickel, electroless palladium, immersion gold (ENEPIG) finished pads assembled using SnPb and SAC305 solders under harmonic vibration loading is examined. ENEPIG test specimens with two thicknesses of palladium were evaluated. Isothermal preconditioning levels at 100°C for 24 hrs and 500 hrs were included to evaluate the impact of intermetalic evolution on the durability of the soldered interconnects. For comparison, tests specimens created with immersion silver (ImAg) finished printed wiring boards were also included. The failure data obtained found the durability of interconnects formed with ENEPIG finish was comparable or better durability than the durability of interconnects formed with ImAg finish irrespective of the solder. The tests indicate that the use of a thicker palladium layer reduced the degradation in durability which occurred from isothermal aging.

Transient Thermal Analysis as a Test Method for the Reliability Investigation of High Power LEDs during Temperature Cycle Tests

Light emitting diodes (LEDs) are today standard and mature light sources. They have several key advantages, like small size, low energy consumption and long lifetime. However, high reliability of the LED system is required to achieve long lifetime of the light source. Thermo-mechanical stress due to temperature cycle causes failure of electronic systems. The electronic component itself or the interconnect device, e.g. printed circuit board (PCB) might fail. In many cases, the weakest link is found to be the solder interconnect between package and the board. Cracking of the interconnect causes an open contact and the system fails. In this paper we compare the existing methods to investigate LED interconnect failures during temperature cycle tests like the simple “light-on-test”, electric resistance measurement and the shear test. We describe and introduce the transient thermal analysis as a measurement method. We present the first reliability data analysis with transient thermal analysis of ceramic high power LED packages on Al-IMS during air to air thermal shock test (−40°C to +125°C) and correlate it with cross sections. We demonstrate the sensitivity of the thermal analysis to detect solder joint failures of the assembly. We compare the results with electric resistance measurements and light on tests and show that the resolution is significantly higher compared to the methods applied today. The sensitivity of the method enables us to detect the crack in a solder joint much earlier than the final failure of the joint, i.e. the open contact.

Electromigration in Lead – Free Solder: A Power IC Perspective

Over the past few years, lead - free solder interconnects have been significantly incorporated into electronic products, and are increasingly found in high performance computing systems and in their associated power electronics. As power and current levels increase within these products, the overall reliability of a lead-free solder based system can be impacted by an increasing risk of finding electromigration (EM) degradation during the product lifetime, especially if the product is operating at higher temperatures and with very high current densities. This paper provides a high-level technical overview of lead-free electromigration and describes the key factors and issues that can influence the EM performance of lead-free interconnects, especially in the environments in which power electronics are typically found.

Electrophoretic Deposition of Carbon Nanotubes for Interconnections in Microelectronics

ABSTRACTCarbon nanotubes (CNTs) have been considered as a promising interconnect material to replace the solder bump used in the flip chip package because of their special electrical, mechanical and thermal properties, which may promote both the performance and reliability of the flip chip packaging. In this paper, electrophoretic deposition (EPD) of CNTs on substrates has been demonstrated for the interconnect application. EPD is a simple, low cost and high throughput process that is capable to produce densely packed film with good homogeneity at low temperature. By altering the electric fields and deposition time during the EPD process, the thickness of the CNTs film could be controlled. In this study, multi-walled carbon nanotubes (MWCNTs) were successfully coated on the various substrates using the EPD method. A highly uniform CNTs microstructure film with thickness over 5 µm was achieved. In addition, the selective depositions of CNTs on the pre-defined bond pads to form CNTs bumps were also accomplished. By employing typical flip-chip bonding technique, high density CNTs bumps were aligned to form a test chip/host substrate interconnects. The electrical conductivity of the CNTs interconnects was carried out using four-point probe measurement. Reliable electrical contacts with linear relationship in the current-voltage (I-V) characteristic suggesting ohmic behaviour were attained. The overall resistances extracted were also relatively low. These superior electrical properties have demonstrated that the CNTs bumps deposited using EPD method is a viable way to serve as an alternative to current metal solder interconnects material such as Sn-Pb alloys. Hence, it offers a promising interconnect application in the quest for device miniaturization in microelectronic industry.

The Role of Pd in Sn-Ag-Cu Solder Interconnect Mechanical Shock Performance

The mechanical stability of solder joints with Pd added to Sn-Ag-Cu alloy with different aging conditions was investigated in a high-G level shock environment. A test vehicle with three different strain and shock level conditions in one board was used to identify the joint stability and failure modes. The results revealed that Pd provided stability at the package-side interface with an overall shock performance improvement of over 65% compared with the Sn-Ag-Cu alloy without Pd. A dependency on the pad structure was also identified. However, the strengthening mechanism was only observed in the non-solder mask defined (NSMD) pad design, whereas the solder mask defined (SMD) pad design boards showed no improvement in shock performance with Pd-added solders. The effects of Sn grain orientation on shock performance, interconnect stability, and crack propagation path with and without Pd are discussed. The SAC305 + Pd solder joints showed more grain refinements, recrystallization, and especially mechanical twin deformation during the shock test, which provides a partial explanation for the ability of SAC305 + Pd to absorb more shock-induced energy through active deformation compared with SAC305.

Decorrelated Feature Space and Neural Nets Based Framework for Failure Modes Clustering in Electronics Subjected to Mechanical Shock

Electronic systems under extreme shock and vibration environments may sustain several failure modes simultaneously. Previous experience indicates that the dominant failure modes experienced by packages in a drop and shock framework are in the solder interconnects including cracks at the package and the board interface, pad cratering, copper trace fatigue, and bulk-failure in the solder joint. In this paper, a method has been presented for failure mode classification using a combination of Karhunen Loeve transform with parity-based stepwise supervised training of a perceptrons. New is the early classification of multiple failure modes in the pre-failure space using supervised neural networks in conjunction with a Karhunen Loeve transform. The feature space has been formed by joint time frequency analysis. Because the cumulative damage may be accrued under repetitive loading with exposure to multiple shock events, the area array assemblies have been exposed to shock and feature vectors constructed to track damage initiation and progression. The error back propagation learning algorithm has been used for stepwise parity of each particular failure mode. The classified failure modes and failure regions belonging to each particular failure mode in the feature space are also validated by simulation of the designed neural network used for parity of feature space. Statistical similarity and validation of different classified dominant failure modes is performed by multivariate analysis of variance and Hotelling's T-square. The results of different classified dominant failure modes are also correlated with the experimental cross sections of the failed test assemblies. The methodology adopted in this paper can perform real-time fault monitoring with identification of a specific dominant failure mode, and is scalable to system level reliability.

Impact of Electrical Current on the Long-Term Reliability of Fine-Pitch Ball Grid Array Packages with Sn-Ag-Cu Solder Interconnects

The interaction between electrical current and the long-term reliability of fine-pitch ball grid array packages with Sn-3.0Ag-0.5Cu (wt.%) solder ball interconnects is investigated. In this study, 0.4-mm fine-pitch packages with 300-μm-diameter Sn-Ag-Cu solder balls are used. Electrical current was applied under various conditions to two different package substrate surface finishes to compare the effects of chemically unmixed and mixed joint structures: a Cu/SAC305/Cu structure and a NiAu/SAC305/Cu structure, respectively. To study the thermal impact on the thermal fatigue performance and long-term reliability, the samples were thermally cycled from 0°C to 100°C with and without current stressing. Based on Weibull plots, the characteristic lifetime was degraded for the mixed joint structure, but little degradation was observed for the unmixed joint structure. The microstructure evolution was observed during constant current stressing and current stressing during thermal cycling. Accelerated intermetallic precipitation depletion at the package-side interface was observed in NiAu/SAC305/Cu structures due to current stressing, which was identified as the potential reason for the degradation in the thermal cycling performance.

Effect of Isothermal Aging and Electromigration on the Microstructural Evolution of Solder Interconnections During Thermomechanical Loading

The effect of different pre-aging treatments on the microstructural evolution of lead-free solder and growth of interfacial intermetallic compound layers under thermal cycling has been investigated in this work. The results show that there are distinct differences in the microstructural changes between samples with no pretreatment, samples that have experienced thermal annealing at 125°C for 750 h before thermal cycling, and those that have had direct current (DC) stressing for 750 h as pretreatment. The microstructural evolution of the solder matrix is rationalized by utilizing the science of microstructures and analysis of the influence of electron flow on the precipitation phenomena. The finite-element method is utilized to understand the loading conditions imposed on the solder interconnections during cyclic stressing. The growth of intermetallic reaction layers is further analyzed by utilizing quantitative thermodynamic calculations coupled with kinetic analysis. The latter is based on the changes in the intrinsic diffusion fluxes of elements induced by current flow and alloying elements present in the system. With this concurrent approach the differences seen in thermal cycling behavior between the different pre-aging treatments can be explained.

Size and constraint effects on interfacial fracture behavior of microscale solder interconnects

The fracture behavior of solder joints has long been an important issue in the reliability evaluation of electronic components and packages. In this study, experimental and finite element methods were used to characterize the interfacial fracture behavior of “Cu-wire/solder/Cu-wire” sandwich-structured microscale Sn–3.0Ag–0.5Cu solder joints with different diameters (100–575μm) and thicknesses (35–325μm) under quasi-static micro-tension loading, with systematic comparison to Sn–37Pb solder joints. Dynamic stress intensity factors for the microcracks in Cu, Sn–3.0Ag–0.5Cu, and Sn–37Pb under pulse tensile loading and high speed propagation were calculated. The numerical simulation results showed that the interface stress intensity factors KII and KI for the crack set at the solder/IMC interface increased with increasing the thickness of the joints from 35μm to ∼125μm, and thereafter decreased and then became stable. With increasing the diameter of the joints, basically KI increases while KII decreases. Under the quasi-static micro-tension loading, the crack driving forces in Sn–3.0Ag–0.5Cu solder joints are lower than that in Sn–37Pb joints, and this means that fracture is less likely to occur in Sn–3.0Ag–0.5Cu solder joints than in Sn-joints. The rapid expansion of a high hydrostatic pressure region may enhance the mechanical performance of interconnects when the diameter-to-thickness ratios of the joints are very large. As the diameter of the solder joints increases, the evolution of the energy release distribution results in a change of the fracture position and mechanism in the interconnects. Compared to Sn–37Pb solder, the Sn–3.0Ag–0.5Cu lead-free solder shows a lower resistance to rapid crack propagation under constant tensile loading.