SOI PIN Research Articles

Temperature and Silicon Film Thickness Influence on the Operation of Lateral SOI PIN Photodiodes for Detection of Short Wavelengths

This work presents an analysis of the temperature influence on the performance of a lateral thin-film SOI PIN photodiodes when illuminated by low wavelengths, in the range of blue and ultra-violet (UV). Experimental measurements performed from 100K to 400K showed that the optical responsitivity of SOI PIN photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations showed the same trends as in the experimental results, and were used both to investigate the physical phenomena responsible for the observed behavior as a function of the temperature as well as to predict the influence of silicon film thickness downscaling on the photodetector performance.

Modeling of Thin-Film Lateral SOI PIN Diodes with an Alternative Multi-Branch Explicit Current Model

We propose the use of an alternative multi-exponential model to describe multiple conduction mechanisms in thin-film SOI PIN diodes with parasitic series resistance over a wide operating temperature range, from 90 to 390 K. This alternative multi-exponential model can be used for semiconductor junctions which exhibit multiple conduction mechanisms with series and shunt resistances. Using Thevenin’s theorem and the Lambert W function, the terminal current is expressed explicitly as a function of the terminal voltage. Its explicit nature allows higher computational efficiency and makes this model better suited for repetitive simulation applications than conventional implicit models. Additionally, direct analytic differentiation and integration are possible. This alternative model is used to describe the I-V characteristics of real SOI PIN diodes.

Thin-Film Lateral SOI PIN Diodes for Thermal Sensing Reaching the Cryogenic Regime

This paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.

Temperature, Silicon Thickness and Intrinsic Length Influence on the Operation of Lateral SOI PIN Photodiodes

This work presents an analysis of the influence of the intrinsic length region (Li) and the thickness of the silicon film (tSi) on the performance of lateral thin-film SOI PIN photodiodes when illuminated by low wavelengths, in the blue and ultraviolet (UV) range. The experimental measurements performed with the wavelengths of 396 nm, 413 nm, and 460 nm in a temperature range of 100 K to 400 K showed that the optical responsivity of the SOI PIN photodetectors has larger dependence on the incident wavelength than on temperatures variation. Two-dimensional numerical simulations showed the same trends as the experimental results as a function of temperature and as a function of wavelength. Numerical simulations were used to investigate the responsivity and total quantum efficiency of PIN SOI photodetectors with intrinsic length region ranging from 5 µm to 30 µm and silicon film thickness ranging between 40 nm to 500 nm. From the results can be concluded that by properly choosing Li and tSi it is possible to optimize PIN SOI photodiodes performance for detecting specific wavelengths.

Enhanced ultraviolet photoresponse in a graphene-gated ultra-thin Si-based photodiode

We present an ultra-thin lateral SOI PIN photodiode with transferred monolayer graphene as the transparent gate, to provide enhanced ultraviolet (UV) performance and mechanical flexibility beyond standard Si-based devices. The device dark current shows intact characteristics after the post-CMOS thinning and graphene transfer processing steps. The device responsivity presents high potential in UV and visible wavelength detections (i.e. within the 200–900 nm range) under monochromatic light illumination. A maximum responsivity of 0.18 A W−1 has been experimentally achieved at 390 nm wavelength and validated by simulation, for a diode with intrinsic length Li of 20 μm. Additionally, the ~5 μm-thick device chip with direct board assembly paves the way towards the development of hybrid flexible electronics.

Carrier Lifetime Measurement in Ultrathin FD-SOI Using Virtual Diodes

In ultrathin fully depleted SOI PIN structures with underlapped gate, the front and back gates can be biased such as to emulate electrostatic diodes. The gate-induced electrons and holes result in a virtual P-N junction in the center of an undoped body. The current–voltage I – V curves are essentially diode-like but reconfigurable via gate voltage tuning. The virtual P-N and P-I-N diodes are used, for the first time, to evaluate the carrier lifetime in ultrathin SOI layers. This paper presents novel experiments and simulations. The transition between recombination and diffusion current in I – V characteristics enables quick lifetime extraction. A more evolved and accurate technique consists in monitoring the reverse recovery current in virtual diodes. This method reveals a very short carrier lifetime in 7-nm-thick SOI layers where surface recombination prevails. This result is confirmed by adapting a P-I-N-diode technique to sub-10 nm films.

Fast recovery SOI PiN diode with multiple trenches

In this paper, a 500V SOI PiN lateral diode is proposed and investigated by simulations and experiments. The proposed structure features multiple deep-oxide trenches (MDOT) arranged in the silicon region. Two DOTs (T1 and T2) locating in the i-layer help to block the cathode-anode voltage (VCA), allowing the diode to shorten its i-layer length. With a similar breakdown voltage (BV) of 560V, the i-layer length is shortened from 47 μm for the conventional diode to 21.9 μm for the proposed MDOT diode. The shortened i-layer leads to a reduced number of stored carriers in the i-layer. Another DOT (T3) is inserted at the anode region of proposed MDOT diode and shorted with P+ anode. T3 acts as a vertical field plate, reshaping the electric potential distribution at the anode region and accelerating the depletion during the reverse recovery process. Thanks to the decreased number of the stored carriers and the accelerated depletion, the reverse recovery time (trr) of the proposed MDOT diode (211 ns) can be decreased by 56.7% compared with the conventional diode (487 ns) at the forward current density of 400 A/cm2 at T = 300 K. The proposed MDOT diode exhibits a better trade-off between forward voltage drop (VF) and reverse recovery time (trr) than the conventional and other reported diodes.

Study of Total Quantum Efficiency of Lateral SOI PIN Photodiodes with Back-Gate Bias, Intrinsic Length and Temperature Variation

: This paper addresses, for the first time, an analysis of the total quantum efficiency of lateral SOI PIN photodiodes with different intrinsic lengths in the 300 to 500 K range simultaneously considering back-gate bias and temperature influences. Introduction: The detection of ultra-violet is used in many applications fields [1,2] with operating temperatures of up 500K. The use of SOI PIN Photodiodes is required to provide high quantum efficiency [3]. These devices consist of a highly-doped P and N regions separated by an intrinsic region (with light P-type residual doping) with length LI (Figure 1). The characterized devices follow the 0.13μm technology from ST described in [6]. They consist of five devices with different intrinsic lengths (LI), but keeping the same total area by changing the numbers of fingers (m), i.e. when LI=1 μm, m=105, when LI= 2μm, m=75, and so on. Experimental Measurements: In Figure 2 the higher temperature is shown to produce an increase in the ITOTAL (UV illumination with λ=387nm and optical power of 0.57μW) mainly due to the thermal generation of carriers [4]. The variation of VBG modifies the operation mode (accumation, depletion or inversion) of the silicon film [5], the accum. mode is obtained for VBG < -10V, the depletion mode occurs when increasing VBG and the current abruptly raises, and then the inv. mode is achieved for VBG>3V. Since the total current can be approximated by the sum of diffusion and generation (drift) currents [7], if the device is operating at lower temp., the generation will dominate, and then the current will be composed by minority carriers which are the electrons. However, for higher temp., the diffusion current dominates, because of the strong thermal generation of carries. Moreover, the diffusion component is composed of majority carriers, which are the holes. This change in the component that dictates the current has an influence when comparing the ratio between the accum. and inv. currents that can be seen in Figure 3. The devices with shorter LI present the higher variations, showing to be more susceptible than the longer ones. So far, only total current was analysed, however Figure 4 shows the dark current as a function of LI for T=375K, and it is possible to see that when the mode of operation is accum., IDARK decreases with LI, while in inv., it increases. This fact can be explained as follows: IDARK is proportional to the size of the depletion region of each device. In accum., there is only the presence of a lateral depletion formed between the intrinsic and N+ region, which is not affected by the LI, but rather by the numbers of fingers. Thus, as the LI increases, m decreases, which results in a decreased total depletion region, so, reducing IDARK level. On the other hand, in inv., beyond the lateral depletion, there is also a vertical depletion region, in the second interface, caused by the VBG, which is highly influenced by LI. This means that, by increasing the intrinsic length, there is a raise in the vertical depletion size, thereby enhancing IDARK. Again, the more negative VD, the higher the current level. Although Figure 4 shows the case for temp. of 375 K, similar behaviour was observed for the other temp. The quantum efficiency (QE) as a function of LI is ploted in Figure 5. The QE is defined as the ratio between the photocurrent and the maximum current that would be generated if there was no kind of loss [8]. It presented almost no variation with VBG for T=300K. Besides that, the maximum QE of 33% was achieved for the device with LI=5μm at room temp. However, for T=500K, the efficiency is affected by VBG in a way that for inv. mode, the QE is inversely proportional to LI, while for accum. mode, it is directly proportional to LI (except for LI=100μ), this last one has the same trend as when T=300K. Still for T=500K, a maximum QE of 56.2% was obtained for LI=1μm in inv. mode and 21.7% for LI=10μm in accum. Conclusions: It was shown that when the device requires operation at higher temp., the best technological choices are the devices with smaller intrinsic lengths in inv. mode of operation because that can achieve 56.2% of QE. While at room temp., the higher QE was found to be 33% for LI=5μm independently of the mode of operation. Figure 1

Study of Total Quantum Efficiency of Lateral SOI PIN Photodiodes with Back-Gate Bias, Intrinsic Length and Temperature Variation

This paper addresses, for the first time, an analysis of the total quantum efficiency of lateral SOI PIN photodiodes with different intrinsic lengths in the 300 to 500 K range simultaneously considering back-gate bias and temperature influences. Experimental results showed that the mode of operation changes the behavior of the devices concerning dark and photocurrents, while the temperature variation produces different trades in quantum efficiency related to the absorption length and the diffusion length variation.

Illuminated to dark ratio improvement in lateral SOI PIN photodiodes at high temperatures

This work presents a study of the illuminated to dark ratio (IDR) of lateral SOI PIN photodiodes. Measurements performed on fabricated devices show a fivefold improvement of the IDR when the devices are biased in accumulation mode and under high temperatures of operation, independently of the anode voltage. The obtained results show that the doping concentration of the intrinsic region has influence on the sensitivity of the diodes: the larger the doping concentration, the smaller the IDR. Furthermore, the photocurrent and dark current present lower values as the silicon film thickness is decreased, resulting in a further increase in the illuminated to dark ratio.

Approximate analytical expression for the tersminal voltage in multi-exponential diode models

We propose a simple approximate solution for the terminal voltage as an explicit function of the terminal current for diodes which need to be modeled by two or more ideal diodes in parallel. As a result, this solution is better suited for repetitive simulation applications than conventional implicit equations because of its inherently higher computational efficiency. Its explicit nature also makes direct analytic differentiation and integration possible. The approximate solution’s applicability has been assessed by parameter extraction and subsequent playback using measured I–V characteristics of lateral thin-film SOI PIN diodes and also using synthetic I–V characteristics of a solar cell.

Operation of Lateral SOI PIN Photodiodes with Back-Gate Bias and Intrinsic Length Variation

This paper presents an analysis of the operation of lateral thin-film SOI PIN photodiodes for the detection of short wavelengths. Experimental measurements were done varying the back-gate bias in order to point out the behavior of the device. The temperature influence was also analyzed in 300K to 500K range. In addition, by using two-dimensional numerical simulations, the intrinsic length (LI) was changed, with the purpose of predicting the performance of this photodetector in more advanced technologies.

Operation of Lateral SOI PIN Photodiodes with Back-Gate Bias and Intrinsic Length Variation

not Available.

Characterization of Thin-Film SOI PIN Diodes from Cryogenic to Above Room Temperatures Using an Explicit I-V Multi-Branch Model

A multi-branch model is proposed to describe multiple conduction mechanisms in thin-film SOI PIN diodes with parasitic series resistance over a wide operating temperature range, from 90 to 390 K. The model is composed of the parallel combination of three branches, each of them incorporating a diode and a series resistance. The model's unique advantage is its explicit nature which allows the terminal current to be continuously expressed as an explicit analytical function of the applied terminal voltage. The resulting explicit equation is convenient for repetitive simulation applications as well as for analytic differentiation and integration, in contrast to conventional models which only allow numerical solutions. The model's suitability has been assessed by parameter extraction and subsequent playback on real SOI PIN diode forward I-V characteristics.

Analysis of Lateral SOI PIN Diodes for the Detection of Blue and UV Wavelengths in a Wide Temperature Range

This work presents an analysis on the performance of lateral thin-film SOI PIN diodes for the detection of short wavelengths, in the range of blue and ultra-violet (UV) wavelengths, as a function of the temperature, reaching the cryogenic regime. Measurements performed for temperatures ranging from 100 K to 400 K showed that the optical responsitivity of these photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations were performed showing the same trends as the experimental data, and were used to predict the influence of silicon film thickness downscaling on the photodetector performance.

Physical modeling of millimetre wave signal reflection from forward biased PIN diodes

This paper examines the DC power requirements of PIN diodes which, with suitable applied DC bias, have the potential to reflect or to permit transmission of millimetre wave energy through them by the process of inducing a semiconductor plasma layer in the I region. The study is conducted using device level simulation of SOI and bulk PIN diodes and reflection modeling based on the Drude conduction model. We examined five diode lengths (60–140μm) and seven diode thicknesses (4–100μm). Simulation output for the diodes of varying thicknesses was subsequently used in reflection modelling to assess their performance for 100GHz operation.It is shown that substantially high DC input power is required in order to induce near total reflection in SOI PIN diodes at 100GHz. Thinner devices consume less DC power, but reflect less incident radiation for given input power. SOI diodes are shown to have improved carrier confinement compared with bulk diodes.

On the Performance of Thin-Film Lateral SOI PIN Diodes as Thermal Sensors in a Wide Temperature Range

This paper presents a study of lateral SOI PIN diodes as temperature sensors in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend this analysis, verifying the accuracy of the existing model.

Characterization of quantum efficiency, effective lifetime and mobility in thin film ungated SOI lateral PIN photodiodes

This paper presents an analytical model of the optical sensitivity and dark current of thin film SOI PIN diodes validated by measurements. This allows us to prove the very good adequacy of thin film SOI for UV-sensing (quantum efficiency in excess of 60% without any anti-reflection coating and dark current lower than pA for a total diode area of 50 × 50 μm 2) and to propose a new method for extracting the effective lifetime and electron, and hole mobilities in SOI thin film ungated structures.