Abstract
In ultrathin fully depleted SOI PIN structures with underlapped gate, the front and back gates can be biased such as to emulate electrostatic diodes. The gate-induced electrons and holes result in a virtual P-N junction in the center of an undoped body. The current–voltage I – V curves are essentially diode-like but reconfigurable via gate voltage tuning. The virtual P-N and P-I-N diodes are used, for the first time, to evaluate the carrier lifetime in ultrathin SOI layers. This paper presents novel experiments and simulations. The transition between recombination and diffusion current in I – V characteristics enables quick lifetime extraction. A more evolved and accurate technique consists in monitoring the reverse recovery current in virtual diodes. This method reveals a very short carrier lifetime in 7-nm-thick SOI layers where surface recombination prevails. This result is confirmed by adapting a P-I-N-diode technique to sub-10 nm films.
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