SOI Nanowire Research Articles

Performance optimization for the sub-22 nm fully depleted SOI nanowire transistors

A comprehensive yet simple design methodology of silicon nanowire MOSFETs is presented. An analytical gate capacitance model for sub-22nm gate length is also proposed to gain insight into design optimization with quantum confinement included. In contrast to conventional bulk device design, this work shows that the wire diameter does not necessarily follow the common stringent scaling rule. An optimal device design window does exist while a moderate wire diameter dimension is suggested without the need of extremely scaled dimension. The nanowire diameter designed at two thirds of gate length minus three times gate oxide thickness is shown to achieve good control of short-channel effects.

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI) substrate is presented. Two-dimensional strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. An improvement of electron mobility in sSOI NW scaled down to 10-nm width is successfully demonstrated (+55 % with respect to SOI NW) due to remaining uniaxial tensile strain. This improvement is maintained even by using hydrogen annealing to form an Omega gate. For short gate length, a strain-induced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> gain as high as +40% at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LG</i> = 45 nm is achieved for a multiple-NW active pattern.

Review of advanced CMOS technology for post-Moore era

The continuous downsizing of device has sustained Moore’s law in the past 40 years. As the power dissipation becomes more and more serious, a lot of emerging technologies have been adopted in the past decade to solve the short channel effect, leakage and performance degradation problems. In this paper, the emerging scaling technologies and device innovations, including high-k/metal gate, strain, ultra-shallow junction, tri-gate FinFET, extremely thin SOI and silicon nanowire FET will be reviewed and discussed in terms of the potential and challenge for post-Moore era.

Current progress in modeling self-heating effects in FD SOI devices and nanowire transistors

In this paper we summarize 6 years of work on modeling self-heating effects in nano-scale devices at Arizona State University (ASU). We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional and the three-dimensional version of the tool) and then we present series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in silicon on insulator technology (SOI). Our simulation results also show that in the smallest devices considered the heat is in the contacts, not in the active channel region of the device. Therefore, integrated circuits get hotter due to larger density of devices but the device performance is only slightly degraded at the smallest device size. This is because of two factors: pronounced velocity overshoot effect and smaller thermal resistance of the buried oxide layer. Efficient removal of heat from the metal contacts is still an unsolved problem and can lead to a variety of non-desirable effects, including electromigration. We propose ways how heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. We also study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel and the self-heating effects. We illustrate the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel.

SOI nanowire for the high-sensitive detection of HBsAg and α-fetoprotein

Silicon-on-isolator-nanowires (SOI-NWs) were used for the label-free, real-time biospecific detection of the hepatitis B marker HBsAg and cancer marker α-fetoprotein (AFP). Specific protein-protein recognition was carried out using individual NWs that were functionalized with antibodies. To solve the problem of non-specific binding of target protein molecules to the sensor element the use of a reference NW with immobilized antibodies against non-target proteins was proposed. Using individual SOI-NW surface functionalization allowed the fabrication of a NW array, containing working NWs and reference NWs within one chip. It was shown that this approach allows us to reach a detection limit up to 10(-14) and 10(-15) M for HBsAg and AFP, respectively. Our investigations also allowed us to reveal the influence of the charged state of the target protein molecules and antibodies in solutions with various pH values on the target protein detection limit. A high sensitivity NW-detector is of interest for the creation of diagnosticums for hepatitis B and for the early stages of cancer diseases.

Silicon-on-Insulator Nanowire Resonators for Compact and Ultra-High Speed All-Optical Wavelength Converters

We present the development of application-specific silicon-on-insulator SOI nanowire ring and racetrack resonators designed to assist semiconductor optical amplifier (SOA)-based all-optical wavelength conversion. We demonstrate the fabrication of fix resonance racetrack resonators exhibiting coupling gaps as low as 160 nm and tunable ring resonators with coupling gaps <; 90 nm. The resonators are cascaded after commercial 40 Gb/s SOAs to realize chirp filtering of the optical data signals through high-resolution spectral sampling. We experimentally demonstrate inverted and non-inverted SOI resonator-assisted all-optical wavelength conversion at 40 Gb/s and 160 Gb/s with power penalties <; 3 dB.

Novel concept for ultracompact polarization splitter-rotator based on silicon nanowires

A novel concept for an ultracompact polarization splitter-rotator is proposed by utilizing a structure combining an adiabatic taper and an asymmetrical directional coupler. The adiabatic taper structure is singlemode at the input end while it becomes multimode at the other end. When light propagates along the adiabatic taper structure, the TM fundamental mode launched at the narrow end is efficiently (close to 100%) converted to the first higher-order TE mode at the wide end because of the mode coupling between them. By using an asymmetrical directional coupler that has two adjacent waveguides with different core widths, the first higher-order TE mode is then coupled to the TE fundamental mode of the adjacent narrow waveguide. On the other hand, the input TE polarization does not change when it goes through the adiabatic taper structure. In the region of the asymmetrical directional coupler, the TE fundamental mode in the wide waveguide is not coupled to the adjacent narrow waveguide because of phase mismatch. In this way, TE- and TM- polarized light are separated while the TM fundamental mode is also converted into the TE fundamental mode. A design example of the proposed polarization splitter-rotator is given by using silicon-on-insulator nanowires and the total length of the device is less than 100μm. Furthermore, only a one-mask process is needed for the fabrication process, which is compatible with the standard fabrication for the regular photonic integrated circuits based on SOI nanowires.

Top-Down Processed SOI Nanowire Devices for Biomedical Applications

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Observation of Coulomb Oscillations with Single Dot Characteristics in Heavy Doped Ultra Thin SOI Nanowires

Nanowire devices with back gate are fabricated in a heavy doped ultra thin SOI layer by electron beam lithography. Regular and periodic Coulomb oscillations with single dot behavior are observed in an appropriate back gate voltage range. The oscillation period can be determined by the back gate capacitance. The role of the back gate can control the electrical characteristics from the multi-dot junction regimes to the single dot junction regimes. These Coulomb oscillations due to single-electron tunneling are not smeared out by thermal vibration energy when the temperature is less than 40 K.

SOI nanowires as sensors for charge detection

The properties of silicon-on-insulator nanowires (SOI NWs) fabricated by means of electron lithography and gas etching of SOI in XeF2 or SF6:CFCl3 have been investigated. The method used to fabricate the nanowires was found to require no additional anneal to be given to the final structure for defect removal after nanostructuring. The sensitivity of SOI NWs to negative protein BSA molecules in the pH 7.4 buffer solution was shown to be as high as 1 femtomoles. The gate characteristics of SOI NWs were used to determine the charge density of particles adsorbed on the NW surface. A charge density of 4.6 × 1011 cm−2 was estimated for a 1 femtomole protein concentration. The combined use of open-channel structures with top gates was employed for determining the charge state of structure surfaces after different chemical treatments. Chemical treatments giving rise to a density of the negative charges on the surface of NWs ranging in the interval (7–23) × 1011 cm−2 were examined. Treatments in methanol (after removal of the native oxide) were found to provide stabilization of the SOI surface over a 3-h interval after the treatments.

Conduction in ultra-thin SOI nanowires prototyped by FIB milling

This work describes a simple yet fast fabrication method to prototype silicon-on-insulator nanowires (SOINW) by using FIB milling and sacrificial oxidation on SOI substrate. Al-gated silicon wires with 8 nm diameter and 50–200 nm length are successfully demonstrated. The Si-wires are heavily implanted with phosphorus in between two oxidation steps, resulting in a film structure in which the hopping conduction mode occurs in the electron accumulation regime. Conduction oscillations are observed in 8 nm diameter Si-wires at room temperature, in contrast with large geometry samples where no oscillations are visible even at low temperature and where the conduction appears as being temperature activated.

Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs

The current conduction process through a nanowire wrap-around-gate, ∼50 nm channel diameter, silicon MOSFET has been investigated and compared with a ∼2 μm wide slab, ∼200 nm thick silicon (SOI) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and gate oxide thickness. The experimental characteristics of the nanowire and planar MOSFETs were compared with theoretical simulation results based on semi-empirical carrier mobility models. The SOI nanowire MOS devices were fabricated through interferometric lithography in combination with conventional I-line lithography. A significant increase (∼3×) in current density was observed in the nanowire devices compared to the planar devices. A number of parameters such as carrier confinement, effects of parallel and transverse field-dependent mobilities, and carrier scattering due to Coulomb effects, acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The electron mobility in the nanochannel increases to ∼1200 cm2/V s compared to ∼400 cm2/V s for a wide slab planar device of similar channel length. Experiments also show that the application of the channel potential from three sides in the nanowire structure dramatically improves the subthreshold slope characteristics.