Performance optimization for the sub-22 nm fully depleted SOI nanowire transistors

Abstract

A comprehensive yet simple design methodology of silicon nanowire MOSFETs is presented. An analytical gate capacitance model for sub-22nm gate length is also proposed to gain insight into design optimization with quantum confinement included. In contrast to conventional bulk device design, this work shows that the wire diameter does not necessarily follow the common stringent scaling rule. An optimal device design window does exist while a moderate wire diameter dimension is suggested without the need of extremely scaled dimension. The nanowire diameter designed at two thirds of gate length minus three times gate oxide thickness is shown to achieve good control of short-channel effects.