Parasitic Capacitance Modeling of Si-Bulk FinFET-Based pMOS

Abstract

FinFET architecture has witnessed great success at commercial 22-nm node and beyond due to its natural immunity of short-channel effects (SCEs) since the past decade. As the critical size scales down further, the parasitic capacitance becomes a crucial bottleneck to gain the device performance. In this article, analytical parasitic capacitance models (including eight components) are established based on real Si-bulk FinFET pMOS. Compared with the prior works, first, the electric field distribution with a small gate voltage perturbation is employed to reveal the capacitance origin and distribution. Second, except for widely studied parameters (spacer thickness and overlap), the key parameters [source and drain (S/D) recess depth, spacer height, and embedded-SiGe (e-SiGe) cavity overfill] are also studied. The later parameters are seldom considered, but they are widely selected as key in-line monitor items in manufacturing due to their sensitivity to device current and parasitic capacitance. In addition, the geometric dependence on parasitic capacitance is performed and verified well by the 3-D Sentaurus Technology Computer Aided Design (TCAD) simulator. The result shows that the analytical capacitance model can capture geometric behavior well, which finally is understood by the breakdown of the total parasitic capacitance.