SOI Nanowire Research Articles

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process.

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

(Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs

This work compares the Drain-Induced Barrier Lowering (DIBL) effect in SOI nanowire transistors. The fin width, length, and temperature influence are experimentally evaluated for junctionless (JL) and inversion mode (IM) nanowire transistors. The results show that DIBL degradation with length reduction is more pronounced in IM nanowires. Although the DIBL might be higher on JL nanowires, its temperature variation has been reduced compared to IM devices.

Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures

This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be discussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-Induced Drain Leakage will also be studied. The experimental results in the whole temperature range confirm that SOI nanowires are an excellent alternative for FinFET replacement in future technological nodes.

Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors’ Mobility Variation Induced by Substrate Bias

Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors’ Mobility Variation Induced by Substrate Bias

Electrical characterization of stacked SOI nanowires at low temperatures

This work presents the electrical characterization of 2-level vertically stacked nanowire MOSFETs with variable fin widths in the temperature range from 93 K to 400 K. The basic electrical properties, such as threshold voltage, subthreshold slope, and carrier mobility are examined in the linear region with low VDS. In sequence, certain analog figures of merit such as the transconductance, the output conductance, and the voltage gain are assessed in saturation.The threshold voltage variation with temperature is linear and slightly increases for wider devices, which was satisfactorily validated by an analytical model for 3D devices. Additionally, the subthreshold slope remains close to the theoretical limit in the whole range of temperatures.The intrinsic voltage gain is weakly temperature-sensitive in the studied range regardless of the fin width. On the other hand, it increases for narrow devices in all temperatures.

Controlling Threshold Voltage of CMOS SOI Nanowire FETs With Sub-1 nm Dipole Layers Formed by Atomic Layer Deposition

In this article, bidirectional control of threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula>) is realized in both n- and p-silicon-on-insulator (SOI) nanowire FETs (NWFETs) by using sub-1 nm atomic-layer-deposited (ALD) dipole layers (Y₂O₃ and Al₂O₃) for the first time. A 0.7 nm Y₂O₃ inserted between bottom native SiO_<i>x</i> (&#x003C; 1 nm) and top HfO₂ (3 nm) can shift the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> by &#x2212;138 and &#x2212;58 mV for n- and p-NWFET, respectively, while 0.7 nm Al₂O₃ can shift the <inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> of n-NWFET by &#x002B;219 mV and p-NWFET by &#x002B;134 mV. The tunability of such a high<i>-k</i> superstructure for the flat band voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {FB}}$ </tex-math></inline-formula>) shift of capacitors and <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift of planar n-SOI FETs are also investigated. Furthermore, to concisely control the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${V}_{\text {FB}}$ </tex-math></inline-formula> as design, capacitors fabricated with quadra-layer (SiO_<i>x</i>/HfO₂/Al₂O₃/Y₂O₃) high<i>-k</i> superstructure were fabricated and 3 mV <inline-formula> <tex-math notation="LaTeX">${V}_{\text {FB}}$ </tex-math></inline-formula> shift is achieved by carefully adjusting the composition of intermixed-dipole layers. This work points out the route to concisely tune the threshold voltage of complementary metal-oxide-semiconductor (CMOS) FETs with the desired direction and strength.

TCAD Evaluation of the Active Substrate Bias Effect on the Charge Transport of Ω-Gate Nanowire MOS Transistors With Ultra-Thin BOX

This work presents an analysis of the application of active substrate bias (or back bias) on the charge transport properties of n-type <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol{\Omega }$ </tex-math></inline-formula> -gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width. Additionally, the influence of back bias on the electrical parameters of these devices is also investigated through DC parameters such as on-to-off-state current ratio and DIBL. The evaluation is conducted by 3D TCAD simulations calibrated with experimental data. The application of negative back bias on nMOS transistors not only shifts the threshold voltage, but also causes mobility degradation due to the negative potential on the channel pushing the charges against the gate oxide interface. On the other hand, when positive back bias is applied, despite the mobility improvement allowed by the back channel’s superior mobility and the front channel’s less compacted inversion layer, at higher substrate bias levels, a strong mobility degradation is observed in the back channel due to the substrate’s high electric field, resulting in reduction of the channel’s overall effective mobility. The application of positive substrate bias degrades the subthreshold slope, leading to smaller on-to-off-state current ratio, as well as the reduced control of channel charges by the gate electrode worsens the DIBL.

Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio (ION/IOFF) = ~106 shows a higher level of electrostatic integrity. At 5 nm LG with optimized spacer dielectric the device exhibits ~5 orders of improvement in IOFF and the improvement is less than ~2 orders at 20 nm LG. Thus, from the result analysis, the spacer dielectrics are essential at lower LG for better performance. For continued scaling, the HfO2 spacer dielectric ensures high performance with the lowest downfall in ION with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si3N4 respectively. With SiO2, Si3N4, and HfO2 spacers the asymmetric spacer ensures an ION/IOFF of ~106 which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes.

Micro-Raman Characterization of Structural Features of High-k Stack Layer of SOI Nanowire Chip, Designed to Detect Circular RNA Associated with the Development of Glioma.

The application of micro-Raman spectroscopy was used for characterization of structural features of the high-k stack (h-k) layer of “silicon-on-insulator” (SOI) nanowire (NW) chip (h-k-SOI-NW chip), including Al2O3 and HfO2 in various combinations after heat treatment from 425 to 1000 °C. After that, the NW structures h-k-SOI-NW chip was created using gas plasma etching optical lithography. The stability of the signals from the monocrine phase of HfO2 was shown. Significant differences were found in the elastic stresses of the silicon layers for very thick (>200 nm) Al2O3 layers. In the UV spectra of SOI layers of a silicon substrate with HfO2, shoulders in the Raman spectrum were observed at 480–490 cm−1 of single-phonon scattering. The h-k-SOI-NW chip created in this way has been used for the detection of DNA-oligonucleotide sequences (oDNA), that became a synthetic analog of circular RNA–circ-SHKBP1 associated with the development of glioma at a concentration of 1.1 × 10−16 M. The possibility of using such h-k-SOI NW chips for the detection of circ-SHKBP1 in blood plasma of patients diagnosed with neoplasm of uncertain nature of the brain and central nervous system was shown.

SOI-FET Snsors for Virus Detection

The recent outbreak of coronavirus disease caused by the respiratory syndrome coronavirus 2 (SARS-CoV-2) has highlighted the urgent need to develop fast and highly sensitive analytical tools and diagnostic devices to detect and study of the fundamental properties viruses and their nucleic acid and protein components [1]. Silicon-on-insulator field-effect transistors (SOI-FETs) based sensors provide the versatile platform for direct detection of biological species as excellent electrical signal converters. These devices have demonstrated applications for label-free, ultra-sensitive, and selective real-time detection of a wide range of biological species, including nucleic acids, proteins and viruses in either single-element or multiplexed formats [2-5]. Dielectrophoresis (DEP) and electro-hydrodynamic techniques are well known as the methods of selection and delivery of analytes to overcome limitations of diffusive transport to sensor elements without additional processing or labeling steps [6].The aim of this study was to investigate the features of the behavior of the viruses when they are indicated by SOI-FET sensors with DEF-control. For this, SOI-FET sensors with lateral DEP-electrodes and multichannel sensors, for comparison, were used. Top-down technology with using optical lithography was applied for sensor fabrication. Devices manufacturing details are described elsewhere [3]. As an analyte, we used nuclear polyhedrosis viruses (NPVs), coronavirus virus-like particles (CVP) and suspension of specific antibodies to the virus created in the Federal research center of Virology and biotechnology "Vector" of Rospotrebnadzor.The results showed that the sensors used in the study provide the subatomolar level of virus detection. DEP-concentration of viruses increase the response of the sensors by factors of 2 to 9 (compared to the response of sensors without DEP control) and allows the false positives can be eliminated. NPVs lose their mobility with prolonged exposure to an alternating field in the sub-MHz range. The DEP-concentration of CVP leads to the formation of crystal-like structures (Fig.1).This study was supported by grant no. 18-29-02091 of the Russian Foundation for Basic Research. Sample preparation of biological materials was done within the framework of the State Task of Rospotrebnadzor.Referencies: WHO Director-General's opening remarks at the media briefing on COVID-19 – 23 April 2021 23 апреля 2021 г.https://www.who.int/director-general/speeches/detail/who-director-general-s-opening-remarks-at-the-media-briefing-on-covid-19-23-april-2021.Patolsky F., Zheng G., Hayden O., Lakadamyali M., Zhuang X., Lieber C. M. Electrical detection of single viruses // Proc. Natl. Acad. Sci. 2004, v. 101. p. 14017-14022.O. V. Naumova, V. M. Generalov, E. G. Zaitseva, A. V. Latyshev, A. L. Aseev, S. A. Pyankov, I. V. Kolosov, G. G. Ananko, A. P. Agafonov, E. V. Gavrilova, R. A. Maksyutov, and A. S. Safatov. Biosensors Based on Soi Nanowire Transistors for Biomedicine and Virusology. Russian Microelectronics, 2021, v. 50, N3, p. 137–145.Ivanov Y.D., Pleshakova T.O., Kozlov A.F., Malsagova K.A., Krohin N.V., Shumyantseva V.V., Shumov I.D., Popov V.P., Naumova O.V., Fomin B.I., Nasimov D.A., Aseev A.L., Archakov A.I. SOI nanowire for the high-sensitive detection of HBsAg and a-fetoprotein. Lab Chip. 2012, v. 12, p. 5104-5111.Dmitrienko E., Naumova O., Fomin B., Kupryushkin M., Volkova A., Amirkhanov N., Semenov D., Pyshnaya I., Pyshnyi D. Surface modification of SOI FET sensors for label-free and specific detection of short RNA analyte. Nanomedicine 2016, v. 11, N 16, p. 2073-2082.Lee S., Roh S.M., Lee E., Park Y., Lee B.C., Kwon Y., Kim H.J., Kim J. Applications of converged various forces for detection of biomolecules and novelty of dielectrophoretic force in the applications(Review). Sensors, 2020, v.20, p.3242. Fig.1 – Optical image of sensor with lateral DEP electrodes after CVP detection. In the left - CVP organized in crystal-like structures under DEP-concentration, in the right (green dots on dark field) - viruses with luminescent labels. S - source, D - drain. G1, G2 - lateral DEP electrodes. Figure 1

Intrinsic Voltage Gain of Stacked GAA Nanosheet MOSFETs Operating at High Temperatures

In the semiconductor industry, the scaling down of devices has always been the driver in order to improve circuit area efficiency and high current drive, leading to the triple gate FinFET, which is the newest technology for high performance applications. However, it is believed that these devices cannot reach the sub 7 nm nodes and the GAA nanowires MOSFETs has emerged as one of the most promising candidates for this technology node, as it presents high density of integration and higher electrostatic control between gate and channel (1-2).The studied devices are GAA silicon nanosheet MOSFETs, fabricated at Imec, Leuven – Belgium, with two stacked channels with the vertical distance between the sheets of 7.5 nm, an EOT of 0.9 nm, a width of 15 nm and a channel length varying from 200nm down to 28nm.The threshold voltage (VTH) as a function of temperature is presented in figure 1, in which it is possible to observe that, VTH is reduced (in absolute value) for both n- and pMOS as temperature increases due to the fermi potential reduction. The VTH variation rate for these devices shows to be better when compared to other technologies, presenting a variation around -0.64 mV/ºC for the p-type, and -0.4 mV/ºC for the n-type, while planar fully depleted SOI devices reach around -0.8 mV/ºC (3), junctionless FinFETs can achieve around -0.94 mV/ºC (4) and bulk nFinFETs present values around -0.67 mV/ºC for narrow fins and -0.92 mV/ºC for wide ones (5).It is possible to see that the subthreshold swing (SS) values (figure2) are very close to the theoretical limit for the MOS technology, except for 28nm channel length pMOS devices, indicating that pMOS is more susceptible to short channel effects (SCEs) than the nMOS counterpart.In figure 3, the Drain Induced Barrier Lowering (DIBL) degrades when the temperature increases. DIBL degradation for both n- and pMOS with temperature are very similar, showing a variation rate of 0.11 mV/V.ºC. It is also important to note that although DIBL is affected by the temperature, the obtained values (except for L=28nm) are very small reaching in the worst case 50mV/V at 200ºC.The transconductance (gmsat) and output conductance (gd) on saturation region of n-type and p-type, showed in figure 4, decreases with increased temperature mainly due to the carrier mobility degradation. Although the gd degradation for L=28nm occurs for both caused by the channel length modulation, the p-type device presents a higher degradation in all range of temperature due to the gate to channel electrostatic coupling as already observed in the SS behavior (figure 2).The intrinsic voltage gain (AV) does not change significantly with temperature due to the compensation between the gm degradation and gd improvement as shown in figure 4. Long p-channel devices present higher Av (gm/gd) than n-type GAA FETs due to the smaller values of gd which is not compensated by the gm degradation. However, for short devices the higher gd degradation results in smaller Av. As said before, AV is calculated considering gmsat and gd and both depend on the mobility, so it is possible to note that AV is barely affected by temperature. Other important highlight is the obtained AV values for the studied GAA MOSFETs that are very high considering other multiple gate MOSFET structures. Both nMOS and pMOS nanosheet devices, with channel length of 100 nm, reach around 42 dB and 50dB respectively, while for bulk FinFETs , junctionless SOI nanowires and W-gate SOI nanowires the values achieved are 34 dB (6), 37 dB (7) and 40 dB (8), respectively, for the same VGT and similar channel length.Even though the longest devices show better SCE immunity and higher AV values, the device with a channel length of 28 nm still shows a good performance. The GAA nanosheet achieves AV of 33 dB and 28 dB, for n and p-type, respectively, while triple gate SOI nanowires, with channel length of 40 nm, and W-gate SOI nanowires, with channel length of 20 nm, presents values around 27 dB (9) and 20 dB (10), respectively. Figure 1

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

This work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20 nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor.

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (IDS) varying the back gate bias (VB), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for VB influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying VB through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on VB for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of VB and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels.

Electrical characterization of vertically stacked p-FET SOI nanowires

This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [1 1 0]- and [1 0 0]-oriented channels, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [1 1 0]- in comparison to [1 0 0]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on ION/IOFF by reducing WFIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [1 1 0]- and [1 0 0]-oriented NWs, respectively.

Design and Operation of CMOS-Compatible Electron Pumps Fabricated With Optical Lithography

We report CMOS-compatible quantized current sources (electron pumps) fabricated with nanowires (NWs) on 300 mm SOI wafers. Unlike other Al, GaAs or Si based metallic or semiconductor pumps, the fabrication does not rely on electron-beam lithography. The structure consists of two gates in series on the nanowire and the only difference with the SOI nanowire process lies in long (40 nm) nitride spacers. As a result a single, silicided island gets isolated between the gates and transport is dominated by Coulomb blockade at cryogenic temperatures thanks to the small size and therefore capacitance of this island. Operation and performances comparable to devices featuring e-beam lithography is demonstrated in the non-adiabatic pumping regime, with a pumping frequency up to 300 MHz. We also identify and model signatures of charge traps affecting charge pumping in the adiabatic regime. The availability of quantized current references in a process close to the 28FDSOI technology could trigger new applications for these pumps and allow to cointegrate them with cryogenic CMOS circuits, for instance in the emerging field of interfaces with quantum bits.

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K

This work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5nm up to quasi-planar MOSFETs 10μm-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10μm and 40nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated.

A Novel Design of a Wideband Digital Vertical Multimode Interference Coupler

A novel wideband vertical multimode interference coupler (MMIC) is proposed. The proposed coupler replaces the conventional core of MMICs with a multilayer waveguide made of silicon and silicon dioxide. The thickness of the silicon layers of this waveguide is modulated to get a linear relation between the propagation constants of the guided modes and their mode number. This modulation suppresses the wavelength dependence of the coupling length, which maximizes the coupler bandwidth. Since the refractive index profile of the multilayer waveguide of the coupler consists of a group of binary refractive index pulses, it is referred to as a digital vertical (DV)-MMIC. Numerical computations demonstrate the ability to design a DV-MMIC which couples more than 75% of optical power between 470 $\;{\text{ nm }} \times {{{ 220}}}\;{\text{ nm}}$ SOI nanowires separated by a vertical height of $3.3\;\mu\text{m}$ over an ultrawide bandwidth of 825 nm.

(Invited) The (R)Evolution of the Junctionless Transistor

Trends in the electronic industry require smaller and smaller components resulting in transistor sizes down to the nano-scale. This is starting to pose significant manufacturing problems. In classical scaled transistors one has to form two junctions, since source and drain regions are separated by channel area with opposite doping polarity. The diffusion of source and drain doping atoms is difficult to control in very short-channel transistors as shown in Figure 1. In all transistors, the diffusion of source and drain impurities into the channel region becomes a bottleneck to the fabrication of very short-channel devices, and very low thermal budget processing techniques must be used [1]. An electrical junction refers to a thermoelectricity junction, a metal-semiconductor junction or a p-n junction (p-type semiconductor to n-type semiconductor junction). Typically, Metal Oxide Semiconductor (MOS) transistors are made using two p-n junctions: the source junction and the drain junction. An n-channel transistor is an N-P-N structure. A p-channel transistor is a P-N-P structure. Very costly techniques are used to minimize this diffusion, but even in the absence of diffusion the statistical variation of the impurity concentration due to ion implantation or other doping techniques can cause device parameter variation problems. There arises therefore, the need to provide a transistor device structure that overcomes the above-mentioned problems. Ideally, it should be possible to completely deplete the semiconductor film of carriers, in which case the resistance of the device becomes quasi-infinite. In a multigate FET (MugFET) the gate electrode is wrapped around a silicon wire, called “finger” or “fin”, forming a wrapping gate structure with excellent control of the channel electrostatics. The excellent gate-to channel coupling allows one to fully deplete the channel region even if it is heavily doped. The junctionless transistor (JNT) is fabricated without source and drain formation process, as the doping type and concentration in the channel region is essentially equal to that in the source and drain, or at least to that in the source and drain extensions [2-9]. These devices are essentially junction-free as shown in Figure 1. JNT is basically a fully depleted accumulation-mode device, consisting of a heavily-doped SOI nanowire resistor with a MOS gate to control current flow. Doping concentration is constant and uniform throughout the device and typically ranges from 1018 and 1020 cm-3. The JNT device can be tuned to normal-off state when the gate work function is properly chosen and the highly doped channel can be fully depleted with no gate bias. As gate voltage is increased, the JNT enters into partially depletion state, and current conducts in the center of the nanowire when VD is supplied, and then at flatband voltage, the depletion region is completely gone. The accumulation starts at the nanowire surface when further raises the VD, which additionally offers an accumulation current, in spite of the bulk current. This talk will first focus on the revolution of the junctionless transistor, focusing on the initial reports and studies in 2010. Then the evolution of the junctionless transistor will be discussed since the early reports in 2010. The variety of studies will be reviewed, as junctionless transistors are being reported in many more materials other than Si, such as Ge and InGaAs [10-11], and very recently in MoS2 [12] and in other transition-metal-dichalcogenide semiconductors. References : [1} Jain SH, et al. Low resistance, low-leakage ultrashallow p+ junction formation using millisecond flash anneals. Electron Devices, IEEE Transactions on. 2005;52:1610-5. [2] Colinge J-P, et al. Nanowire transistors without junctions. Nat Nanotechnol. 2010;5:225-9. [3] Kranti A, et al. Junctionless nanowire transistor (JNT): Properties and design guidelines. Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European: IEEE; 2010. p. 357-60.[4] Lee C-W, et al., Junctionless multigate field-effect transistor. Appl Phys Lett. 2009;94:053511--2. [5] Lee C-W, et al. Performance estimation of junctionless multigate transistors. Solid State Electron. 2010;54:97-103. [8] Colinge J-P, et al. Reduced electric field in junctionless transistors. Appl Phys Lett. 2010;96:073510--3. [9] Colinge J, et al. Junctionless nanowire transistor (JNT): Properties and design guidelines. Solid State Electron. 2011;65:33-7. [10] Yu, R., et al., “Impact ionization induced dynamic floating body effect in junctionless transistors”, (2013) Solid State Electronics, 90, pp. 28-33. [11] Yu, R., et al.. “Device design and estimated performance for p-type junctionless transistors on bulk germanium substrates” (2012) IEEE Transactions on Electron Devices, 59 (9), art. no. 6226451, pp. 2308-2313 [12] Das, S., et al.., “Nb-doped single crystalline MoS2 field effect transistor”, Appl. Phys. Lett. 106, 173506 (2015). Figure 1

A Review on Evolution, Current Trends and Future Scope of MEMS Piezoresistive Pressure Sensor

Piezoresistive pressure sensors are the first MEMS devices to be commercialized. They work on the principle of change in resistivity of materials due to applied pressure. Literature reports lot of work and development in this area of sensing mechanisms. This paper provides a review on evolution of these sensors right from thin metal film based technology to the semiconductor technology. The paper presents the current trends in the design and use of piezoresistive pressure sensor. The paper also presents the future scope form these sensors which, will be around the extensive use of materials like SOI, SiC, DLC, CNT and Silicon Nanowires.

Silicon–germanium nanowire tunnel-FETs with homo- and heterostructure tunnel junctions

Experimental results on tunneling field-effect transistors (TFETs) based on strained SiGe on SOI nanowire arrays are presented. A heterostructure SiGe/Si TFET with a vertical tunnel junction consisting of an in situ doped SiGe source and a Si channel with a minimum inverse subthreshold slope of 90mV/dec is demonstrated. An increase in tunneling area results in higher on-current. The in situ doped heterojunction TFET shows great improvement compared to a homojunction SiGe on SOI nanowire design with implanted junctions. Temperature dependent measurements and device simulations are performed in order to analyze the tunnel transport mechanism in the devices.