Soft-core Processor Research Articles

Template attack on SPA and FA resistant implementation of Montgomery ladder

Hardware implementations of the well-known Rivest–Shamir–Adleman (RSA) algorithm have been shown to be vulnerable to power and fault analysis (FA) attacks. To implement protected designs of RSA-Chinese remainder theorem in embedded devices, like smart cards or RFIDs, the one needs to find solutions which require less computations as well as incurs low storage overheads. One such efficient scheme was proposed by Joye et al. in CHES'02 and it was claimed to be secure against both simple power analysis (SPA) and FA attacks. In this study, the authors demonstrate a template attack (TA) against Joye's countermeasure and show that the scheme can be broken with a low number of power traces. In addition, the authors report the experimental results of the proposed attack against an implementation of Joye's scheme on a Xilinx Microblaze soft-core processor of SASEBO-W standard side-channel analysis board. The authors used least squares support vector machine (LS-SVM) based binary classifiers to analyse the collected power traces. The authors also describe the potential threat posed by cache timing attacks on Joye's ladder in presence of a concurrently running spy process and outline a probable countermeasure to the posed attacks.

A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

We present a new type of soft-core processor called the “Data-Flow Soft-Core” that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing based on data-flow instructions rather than control flow instructions. As a result, during an execution on the accelerator of the Data-Flow Soft-Core, both partial data and instructions are eliminated as traffic for load and store activities. Data-flow instructions serve to describe a program and to dynamically change the context of a data-flow program graph inside the accelerator, on-the-fly. Our proposed design aims at combining the performance of a fine-grained data-flow architecture with the flexibility of reconfiguration, without requiring a partial reconfiguration or new bit-stream for reprogramming it. The potential of the data-flow implementation of a function or functional program can be exploited simply by relying on its description through the data-flow instructions that reprogram the Data-Flow Soft-Core. Moreover, the data streaming process will mirror those present in other FPGA applications. Finally, we show the advantages of this approach by presenting two test cases and providing the quantitative and numerical results of our evaluations.

Field programmable gate array–based servo control integrated chip for a six-axis articulated robot manipulator

The objective of this article is to build a field programmable gate array–based six-axis servo control integrated chip which can integrate the function of a motion trajectory planning and the function of six position/speed/current servo controllers into one integrated chip. In the work, first, a mathematical modeling of a robot manipulator with the actuator using permanent magnet synchronous motor is derived. Second, the proportional controller in the position loop, a proportional–integral controller in the speed loop and a vector controller in the current loop for each axis are applied. Third, a system on a programmable chip) technology which comprises an Altera field programmable gate array chip and an embedded soft-core Nios-II processor is considered to develop the proposed servo control integrated chip. However, in the servo control integrated chip, it has two modules. The first module is an embedded soft-core Nios-II processor which is used to generate the motion trajectory planning by software. The second module presents a six-axis servo controller intellectual property by hardware which is applied to execute six position/speed/current controllers. Therefore, the function of a motion trajectory command and the function of six position/speed/current servo controllers for a six-axis robot manipulator can be integrated into one field programmable gate array. Finally, to verify the effectiveness and correctness of the proposed field programmable gate array–based servo control integrated chip, a six-axis robot manipulator is applied and some experimental results are demonstrated.

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion.

Soft Core Processor Generated Based on the Machine Code of the Application

Currently embedded system designs aim to improve areas such as speed, energy efficiency and the cost of an application. Application-specific instruction set extensions on reconfigurable hardware provide such opportunities. The article presents a new approach for generating soft core processors that are optimized for specific tasks. In this work, we describe an automatic method for selecting custom instructions for generating software core processors that are based on the machine code of the application program. As the result, a soft core processor will contain the logic that is absolutely necessary. This solution requires fewer gates to be synthesized in the field programmable gate arrays (FPGA) and has a potential to increase the speed of the information processing that is performed by the system in the target FPGA. Experiments have confirmed the correct operation of the method that was used. After the reduction mechanism was enabled, the total number of slices blocks that were occupied decreased to 47% of its initial value in the best case for the Xilinx Spartan3 (xc3s200) and the maximum frequency increased approximately 44% in the best case for Xilinx Spartan6 (xc6slx4).

Computational architectures for sonar array processing in autonomous rovers

This paper presents design of novel embedded computational architectures for real time, in-motion mapping based on ultrasound sensors for use in resource constrained autonomous rovers. Autonomous rovers are a class of real time systems that are constrained for size, weight, on-board computational resources and power. Embedded computing architectures designed for implementing the mapping and navigational algorithms must optimize the use of these resources. In the process of map generation, raw sensor data obtained from an array of ultrasound sensors is filtered for sensor noise using probabilistic sensor model, and probabilistic data fusion methods are employed for spatial and temporal correlation of data for improving the map. In this paper, we present a System-on-Chip design based design space exploration of embedded computational architectures for implementation on field programmable gate arrays. We seek to exploit system level, region level and sensor level parallelism in the mapping algorithm for enhancing the throughput. Design space exploration is carried out by employing existing soft core processors, designing custom co-processors and data path modules and integrating them using parallel and pipelined data flow approaches. Results of mapping a test area on all the architectures are compared to characterize the performance and suitability of the proposed architectures.

Hybrid real-time operating systems: deployment of critical FreeRTOS features on FPGA

Performance and determinism are two critical metrics in most embedded systems with real-time requirements. Owing to the complexity of current embedded systems, along with increased application demands, real-time operating systems (RTOSs) have become a de facto solution providing specific services to the system tasks. However, this extra layer, which abstracts the hardware from the software, makes it harder for a system to achieve good performance and determinism. To ease the impact of a RTOS in the system, RTOS run-time services are offloaded to the hardware layer. This paper presents a hybrid RTOS implementation, where several critical RTOS services were migrated from software to hardware, improving system latency and predictability. Special focus was given to the RTOS scheduler and to the mutexes handling subsystem. The developed hardware accelerators were synthesised on a field-programmable gate array (FPGA), exploiting the point-to-point fast simplex link (FSL) bus to interconnect to the Xilinx Microbaze soft-core processor. Our approach shows that hybrid RTOS has a better performance and predictability when compared to its software-only version.

Multiprocessor systems based on FPGA for receiving and processing data from the position sensors of the manipulator elements with controlled bending

Key moments of technique of reception and processing of information from the MEMS position sensors in the information system of the manipulator built on the basis units with controlled bend is discussed in detail. The differences in the procedure for construction of multiprocessor information systems based on the new programmable logic integrated circuits large capacity which provide the use of soft-core processors is presented too. The results of qualitative comparison of the solutions obtained by use state machine circuits and schemes based on soft-processors is shown. As an example, consider the structure developed multiprocessor information system and variants of its hardware and structural implementation.

FPGA Prototype Implementation of Digital Hearing Aid from Software to Complete Hardware Design

The design and implementation of digital hearing aids requires a detailed knowledge of various digital signal processing techniques used in hearing aids like Wavelet Trans-forms, uniform and non-uniform Filter Banks and Fast Fourier Transform (FFT). In this paper the design and development of digital part of hearing aid is divided into three different phases. In the first phase review and Matlab simulation of various signal processing techniques used in the digital hearing aids is presented. In the second phase a software implementation was carried out and the firmware was designed for the Xilinx Microblaze softcore processor system. In the third phase everything was moved into hardware using VHDL hardware description language. The implementation was done on Xilinx Field Programmable Gate Array (FPGA) Development Board.

Hybrid real-time operating systems: deployment of critical FreeRTOS features on FPGA

Performance and determinism are two critical metrics in most embedded systems with real-time requirements. Owing to the complexity of current embedded systems, along with increased application demands, real-time operating systems (RTOSs) have become a de facto solution providing specific services to the system tasks. However, this extra layer, which abstracts the hardware from the software, makes it harder for a system to achieve good performance and determinism. To ease the impact of a RTOS in the system, RTOS run-time services are offloaded to the hardware layer. This paper presents a hybrid RTOS implementation, where several critical RTOS services were migrated from software to hardware, improving system latency and predictability. Special focus was given to the RTOS scheduler and to the mutexes handling subsystem. The developed hardware accelerators were synthesised on a field-programmable gate array (FPGA), exploiting the point-to-point fast simplex link (FSL) bus to interconnect to the Xilinx Microbaze soft-core processor. Our approach shows that hybrid RTOS has a better performance and predictability when compared to its software-only version.

Enabling PGAS Productivity with Hardware Support for Shared Address Mapping

Due to its rich memory model, the partitioned global address space (PGAS) parallel programming model strikes a balance between locality-awareness and the ease of use of the global address space model. Although locality-awareness can lead to high performance, supporting the PGAS memory model is associated with penalties that can hinder PGAS’s potential for scalability and speed of execution. This is because mapping the PGAS memory model to the underlying system requires a mapping process that is done in software, thereby introducing substantial overhead for shared accesses even when they are local. Compiler optimizations have not been sufficient to offset this overhead. On the other hand, manual code optimizations can help, but this eliminates the productivity edge of PGAS. This article proposes a processor microarchitecture extension that can perform such address mapping in hardware with nearly no performance overhead. These extensions are then availed to compilers through extensions to the processor instructions. Thus, the need for manual optimizations is eliminated and the productivity of PGAS languages is unleashed. Using Unified Parallel C (UPC), a PGAS language, we present a case study of a prototype compiler and architecture support. Two different implementations of the system were realized. The first uses a full-system simulator, gem5, which evaluates the overall performance gain of the new hardware support. The second uses an FPGA Leon3 soft-core processor to verify implementation feasibility and to parameterize the cost of the new hardware. The new instructions show promising results on all tested codes, including the NAS Parallel Benchmark kernels in UPC. Performance improvements of up to 5.5× for unmodified codes, sometimes surpassing hand-optimized performance, were demonstrated. We also show that our four-core FPGA prototype requires less than 2.4% of the overall chip’s area.

The Soft Core Processors: A Review

The Soft Core Processors: A Review

Design of NIOS II Soft-Core based Partial Reconfiguration Controller in FPGA for MPSoC Design

Recent advancement and research in FPGA has led to the development of energy optimization techniques and runtime partial reconfiguration in FPGA. This work describes an effective approach for power reduction techniques in FPGA based Multiprocessor system-on-Chip (MPSoC) platform and it works on partial reconfiguration technique during runtime. Partial reconfiguration is implemented to reconfigure only a part of FPGA dynamically and other parts of the device continues there operation undisturbed. NIOS II soft-core processor is programmed as control processor to perform reconfiguration partially and also it manages the dynamic power optimization process. This control process is further configured for clockgating which works on a FPGA logic element and cut down a substantial part of dynamic power dissolution in FPGA. Proposed power optimized low power MPSoC is implemented using ALTERA cyclone III FPGA and its power analysis is performed and summarized.

Single Chip Embedded System Solution: Efficient Resource Utilization by Interfacing LCD through Softcore Processor in Xilinx FPGA

This paper presents a customized application in term of LCD interfacing through soft-core microcontroller by implementing its control circuitry in FPGA. Therefore optimum efficiency is achieved. This provide the single chip solution by replacing conventional model which contain separate microcontroller circuit, therefore the efficient resource utilization of FPGA is made, day by day as an increase in the complexity of Embedded system design thus gives many advantages over conventional designed processors such as platform independence, less cost, flexibility and greater immunity to obsolescence. Index Terms—FPGA, LCD interfacing, soft-core microcontroller e.t.c.

NIOS II Based Secure Test Wrapper Design for Testing Cryptographic Algorithms

<p>Cryptographic algorithms need infrastructure for testing them against security attacks. Normally many methods are proposed for testing these cryptographic primitives. Normal designs cannot be applied to all types of cryptographic chips. Usually build in self test is applied for the intellectual property chips for testing them. But it suffers from many problems such as side channel attack, backholes, high area overhead, etc.., to overcome all these drawbacks test wrapper is designed and tested using NIOS II economy soft core processor. NIOS II is utilized as the soft core processor and cryptographic algorithms are executed. RTL view of these cryptographic circuits is described. Synthesis result shows the chip planner view of the circuits and the area required for the logic elements. NIOS II soft-core processors perform well for testing the cryptographic algorithms. Results with respects to area optimization, memory and speed are discussed. The logic components required for design using NIOS II is optimized. Memory required is also less compare to other processors. Area required is optimized using NIOS II processor and it is flexible for design of complex circuits.</p>

DEVELOPMENT OF SOFTCORE PROCESSOR

Designing of softcore processor on FPGA is based on software hardware co design. A soft-core processor is a hardware description language (HDL) model of a specific processor (CPU) that can be customized for a given application and synthesized for an ASIC or FPGA target. Embedded Systems which performs specific application using components having hardware and software together is known as embedded system. With hardware design getting complicated day by day, using of software tools for designing the system and testing has made the necessity of today’s technology. Due to the reduced size and greater complexity of hardware models, it requires a higher technological tool for simulation to satisfy the needs of the designers. The more efficient the simulator, complexity in the hardware model can be easily executed in small intervals of time, resulting in design product in a stipulated time intervals. The design of soft core processor system involves strict performance involving area, time, power, cost constraints. Advantages of Softcore processor design improves in design quality reduce integration and test time, supporting growing complexity of embedded system, processor cores, high level hardware synthesizing capabilities, ASIC/FPGA development and platform independence. Xilinx microblaze softcore processor support package allows to create mixed Hardware Software application using micro blaze processor. These processors are called as soft-core processor. Soft IP core of Xilinx micro blaze can be used on series of FPGA.

Design of Dual-Core Processor Industry Robot Controller

The functions of the robot controller are arithmetic operations and motion control, and the common robot is the secondary robot microcontroller control system of industrial PC+ microcontroller. In this paper, two Nios II soft-core processor are designed in an FPGA chip to achieve the dual function of the robot controller with the features of program- mable and being easy to implant. The requirements of robot controllers integration and miniaturization are solved by the method, and has good openness and real-time. The designs of the controller hardware and software systems are described, and the dual-core controller is used in multi-joint robot servo control. The experimental results show that the robot con- troller system is reasonable and feasible.

Safe Dynamic Reshaping of Reconfigurable MPSoC Embedded Systems for Self-Healing and Self-Adaption Purposes

Multiprocessor system-on-chip (MPSoC) architectures are a huge challenge in embedded system design. This situation arises from the fact that available MPSoCs and related designs flows are not tailored to the specific needs of embedded systems. This work demonstrates how to provide self-healing properties in embedded MPSoC design. This is achieved by combining the features of a generic approach to create virtualizable MPSoCs out of off-the-shelf embedded processors with a methodology to derive system configurations, such as task-processor bindings, which are optimal in terms of safety and execution time. The virtualization properties enable a reshaping of the MPSoC at runtime. Thus, system configurations may be exchanged rapidly in a dynamic fashion. As a main result of this work, embedded multiprocessor systems are introduced, which dynamically adapt to changing operating conditions, possible module defects, and internal state changes. We demonstrate the figures of merit of such reconfigurable MPSoC embedded systems by means of a complex automotive application scenario mapped to an FPGA featuring a virtualizable array of eight soft-core processors.

Designing of Soft Core Processor System with Direct Memory Access (DMA) Mode

A soft core processor system is constructed using embedded design techniques and it is configured on Field Programmable Gate Arrays (FPGAs). The system is accommodated to act with Direct Memory Access (DMA) mode using suitable Xilinx Intellectual Property (IP) core. A dual data rate synchronous dynamic random access memory (DDR_SDRAM) with 64 Mbyte capacity is introduced to the system and accessed by the DMA controller.The controller is performed to transfer programmable quantity of data from source address to destination address without intervention of the processor. Spartan-3E slice is used and programmed using Xilinx Platform Studio (XPS)which is provided by Xilinx integrated software environment at (ISE 10.1). The system performance is tested by transferring data from matlab media to the DDR_SDRAM and vice-versa, mat lab 2012a version software is used for this type of data transfer.

Design of a General Purpose 8-bit RISC Processor for Computer Architecture Learning

Computers are becoming indispensable for manipulating most everyday consumer products, ranging from communications and domestic electronics to industrial processes monitoring and control. High performance computer design is not only subject to the technology used for its implementation, it is also a matter of efficient training. The skills that must prevail in a good computer designer come from the type of courses taken and the tools employed during them. This work shows the design of an 8-bit RISC soft-core processor dedicated for a complete understanding of computer architecture. We consider this Processor an effective hands-on training solution for the comprehension of a computer from its lowest level up to testing.