Design of NIOS II Soft-Core based Partial Reconfiguration Controller in FPGA for MPSoC Design

Abstract

Recent advancement and research in FPGA has led to the development of energy optimization techniques and runtime partial reconfiguration in FPGA. This work describes an effective approach for power reduction techniques in FPGA based Multiprocessor system-on-Chip (MPSoC) platform and it works on partial reconfiguration technique during runtime. Partial reconfiguration is implemented to reconfigure only a part of FPGA dynamically and other parts of the device continues there operation undisturbed. NIOS II soft-core processor is programmed as control processor to perform reconfiguration partially and also it manages the dynamic power optimization process. This control process is further configured for clockgating which works on a FPGA logic element and cut down a substantial part of dynamic power dissolution in FPGA. Proposed power optimized low power MPSoC is implemented using ALTERA cyclone III FPGA and its power analysis is performed and summarized.