Soft-input Soft-output Research Articles

The design and implementation of TPC encoder and decoder

Based on the analysis and simulation of TPC codec principle and iteration decoding algorithm based on Chase 2, the design and implementation methods of TPC encoder and decoder are presented in this paper. In particular, circuit design and implementation flow of soft-input soft-output modified method in decoder algorithm and iteration decoding are analyzed. Aiming at (64,57,4) TPC, when the iteration times is 3 and the uncertain position number is 3, simulation and implementation results show that at least 6.8dB encoding gain can be obtained under the condition of BER=10−6

Distributed Soft-Input Soft-Output Coding for Two-Way Wireless Relay Networks

In this letter, we propose a distributed soft-input soft-output (SISO) coding scheme for a two-way relay network. Novel SISO convolutional encoders are developed and new code design for distributed SISO encoding is derived for the proposed encoder. The simulation results show that our proposed distributed SISO encoding can bring considerable distributed coding gains compared to the conventional soft information forwarding.

Multimode Radix-4 SISO Kernel Design for Turbo/LDPC Decoding

To increase the quality of wireless transmission, wireless communication systems employ advanced forward error correction codes such as turbo codes and low-density parity-check (LDPC) codes. To achieve smooth transition between turbo and LDPC decoding in different communication standards, we propose a VLSI design of a multimode radix-4 soft-input soft-output (SISO) kernel in this paper. The proposed radix-4 SISO kernel composed of three recursive processing elements alternatively employs a radix-4 forward–backward algorithm for LDPC decoding and a radix-4 single-binary/double-binary enhanced max-log-maximum a posteriori probability algorithm for turbo decoding by efficiently sharing computational units. The proposed radix-4 SISO kernel achieves an area reduction of 21.8% when compared with the uncombined SISO kernels for alternatively decoding the turbo and LDPC codes. The proposed radix-4 SISO kernel is verified by implementing it in an application-specific integrated circuit of 0.45 $\mathrm{mm}^{2}$ core area by using a 90-nm CMOS process with a maximum area efficiency of 10.65 bits/ $\mathrm{mm}^{2}$ . In addition, the throughput rates of the long-term evolution and worldwide interoperability for microwave access schemes for both LDPC and turbo decoding can be achieved using eight proposed radix-4 SISO kernels.

Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems

This brief presents two types of distributed cyclic redundancy check (CRC) architecture for a high-radix parallel turbo decoder in LTE/LTE-advanced communication systems. The conventional CRC architecture in the parallel turbo decoder requires both huge timing overhead and energy waste since the CRC of the message is calculated after completion of the soft-input soft-output (SISO) decoding process or concurrently with the next SISO decoding, even though the message is already confirmed for its integrity. The distributed CRC architecture proposed in this brief computes the CRC while the message is decoded separately, and it can provide the stopping signal to the decoder with negligible computing latency after completion of the SISO decoding process. The two proposed architectures are based on Galois field arithmetic and implemented in a 65-nm CMOS process where various block sizes, degrees of parallelism, and radix numbers of the high-radix SISO decoder are supported.

Efficient Soft-Input Soft-Output MIMO Chase Detectors for Arbitrary Number of Streams

We present novel soft-input soft-output (SISO) multiple-input multiple-output (MIMO) detectors based on the Chase detection principle [1] in the context of iterative and decoding (IDD). The proposed detector complexity is linear in the signal modulation constellation size and the number of spatial streams. Two variants of the SISO detector are developed, referred to as SISO B-Chase and SISO L-Chase. An efficient method is presented that uses the decoder output to modulate the signal constellation decision boundaries inside the detector leading to the SISO detector architecture. The performance of these detectors significantly improves with just a few number of IDD iterations. The effect of transmit and receive antenna correlation is simulated. For the high-correlation case, the superiority of SISO B-Chase over the SISO L-Chase is demonstrated.

Block Markov Superposition Transmission of Repetition and Single-Parity-Check Codes

This letter presents a method to construct a family of codes with rate K/N(K = 1,2,...,N - 1) for any given integer N > 1. This family of codes, referred to as RSPC codes for short, consist of the repetition (R) code, the single-parity-check (SPC) code and the codes obtained by time-sharing between the R code and the SPC code. The RSPC codes have extremely simple encoding and soft-input soft-output (SISO) decoding algorithms, hence can be integrated into the recently proposed block Markov superposition transmission (BMST) system. The BMST introduces memory across short codes by spatially coupling the generator matrices of the short codes. A distinguished feature of the BMST system is the simple relation between the asymptotic coding gain and the spatially coupling depth (encoding memory). Furthermore, the BMST-RSPC codes can share a pair of easily reconfigurable encoder and decoder. Simulation results show that the BMST-RSPC codes perform well (within one dB away from the corresponding Shannon limits) in a wide range of code rates.

A Dominance-Based Soft-Input Soft-Output MIMO Detector With Near-Optimal Performance

Iterative detection-and-decoding for multi-input multi-output (MIMO) communication systems require a soft-input soft-output (SISO) detection algorithm, which, in the optimal formulation, is well known to be exponentially complex in the number of transmitting antennas. This paper presents a novel SISO detector for MIMO systems, named SISO king decoder. It is a tree-search branch-and-bound algorithm, which exploits the properties of the channel matrix and the a-priori information on the transmitted bits to reduce the overall computational complexity. The proposed algorithm is compared with the SISO single tree-search sphere decoder [1]. Simulation results are provided to show the complexity reduction without relevant performance loss in terms of bit-error rate.

Adaptive switching detection algorithm for iterative‐MIMO systems to enable power savings

AbstractThis paper attempts to tackle one of the challenges faced in soft input soft output Multiple Input Multiple Output (MIMO) detection systems, which is to achieve optimal error rate performance with minimal power consumption. This is realized by proposing a new algorithm design that comprises multiple thresholds within the detector that, in real time, specify the receiver behavior according to the current channel in both slow and fast fading conditions, giving it adaptivity. This adaptivity enables energy savings within the system since the receiver chooses whether to accept or to reject the transmission, according to the success rate of detecting thresholds. The thresholds are calculated using the mutual information of the instantaneous channel conditions between the transmitting and receiving antennas of iterative‐MIMO systems. In addition, the power saving technique, Dynamic Voltage and Frequency Scaling, helps to reduce the circuit power demands of the adaptive algorithm. This adaptivity has the potential to save up to 30% of the total energy when it is implemented on Xilinx®Virtex‐5 simulation hardware. Results indicate the benefits of having this “intelligence” in the adaptive algorithm due to the promising performance‐complexity tradeoff parameters in both software and hardware codesign simulation.

Block-Processing Soft-Input Soft-Output Demodulator for Coded PSK Using DCT-Based Phase Noise Estimation

This paper considers the detection of coded phaseshift keying signals subjected to additive white Gaussian noise and oscillator phase noise. We propose a detector that partitions the received frame into smaller blocks and models the unknown phasor variations over each block as a truncated discrete cosine transform (DCT) expansion. Detection and decoding are iteratively performed between a soft-input soft-output (SISO) demodulator, a SISO demapper, and a SISO decoder based on the sum-product algorithm and the factor graph framework, whereas the expectation-maximization algorithm is used in the demodulator for the DCT coefficients estimation. The resulting demodulator is shown to have an excellent performance/complexity tradeoff and to be well-suited for parallel processing on multiple cores.

Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems

Turbo decoders for modern wireless communication systems have to support high throughput over a wide range of code rates. In order to support the peak throughputs specified by modern standards, parallel turbo-decoding has become a necessity, rendering the corresponding VLSI implementation a highly challenging task. In this paper, we explore the implementation trade-offs of parallel turbo decoders based on sliding-window soft-input soft-output (SISO) maximum a-posteriori (MAP) component decoders. We first introduce a new approach that allows for a systematic throughput comparison between different SISO-decoder architectures, taking their individual trade-offs in terms of window length, error-rate performance and throughput into account. A corresponding analysis of existing architectures clearly shows that the latency of the sliding-window SISO decoders causes diminishing throughput gains with increasing degree of parallelism. In order to alleviate this parallel turbo-decoder predicament, we propose a new SISO-decoder architecture that leads to significant throughput gains and better hardware efficiency compared to existing architectures for the full range of code rates.

MMSE SQRD based SISO detection for coded MIMO-OFDM systems

In this paper, we propose a minimum mean square error (MMSE) sorted QR decomposition (SQRD) based soft-input soft-output (SISO) detection algorithm for coded multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems. The proposed detection is derived from the SISO MMSE detection, which is a popular detection strategy for iterative receivers. For each transmitted symbol in the proposed detection, a soft successive interference cancellation (SIC) is performed based on a posteriori probabilities of past detected symbols. Simulation results show that the proposed detection, while needing less computational efforts, achieves significant performance gain compared with the SISO MMSE detection.

Re-configurable Optimized Area Turbo Decoder for Wireless Applications

Today, the wireless communication is an emanating requirement of day to day process. Due to the noisy environment in wireless communication there is a need of coding system, which can provide high data rate with error free communication. The turbo codes also known as Parallel Convolutional Concatenated Code (PCCC) provides high data rate with bit error rate performance improvement in communication system. With the advent demand of miniaturization, an area efficient turbo decoder of constraint length 3 is proposed in this paper. The turbo decoder used a single SISO (Soft Input Soft Output) decoder architecture in this paper to reduce the area consumption. The SOVA (Soft Output Viterbi Algorithm) is used as a decoding algorithm in SISO decoders. It is based on two step algorithm. The proposed design is simulated using Matlab and synthesized on Xilinx Virtex-2p (xc2vp30-ff896-5) FPGA. The performance of proposed Turbo decoder will be compared for FPGAs in terms of number of slice Flip-flops, LUTs and frequency. The Synthesis results show a 3% improvement in the utilized no. of slice flip-flop and 49% improvement in terms of frequency.

Vlsi Architecture of Mimo Detector Using Fixed Complexity Sphere Decoding

Fixed Sphere Decoding is a near optimum tree search detection technique for the spatial multiplexing scheme. The algorithm performs a fixed number of operations to detect the signal independent of the noise level and channel conditions. In this paper, a Soft Input Soft Output Fixed Complexity Sphere Decoding algorithm is proposed for the MIMO receiver using 16 QAM modulation scheme. As the system performance was far from the channel capacity limit, MIMO channel could not support higher spectral efficiencies. Therefore, to obtain power efficiency very close to the Shannon limit, Turbo codes are implemented in MIMO system and provide higher spectral efficiency. The proposed FSD detector is capable of providing a throughput of 1.18 Gbits/s with a critical path delay of 9.603 ns.

개선된 터보 등화기의 설계와 성능 평가

본 논문에서는 단일 반송파 시스템에서 LDPC(low density parity check) 부호와 LMS(least mean square) 알고리즘을 이용한 적응 등화기를 사용한 시스템에서 간단한 계산을 통한 궤환 신호를 생성하여 성능을 향상 시키는 개선된 터보 등화기를 제안한다. LDPC부호는 오류를 정정하는데 있어서 매우 좋은 성능을 보인다. 그러나 LDPC 부호는 열악한 환경에서 좋은 성능을 내기 위하여 긴 패리티 검사행렬을 사용하고 LDPC 부호의 반복을 증가시켜 계산량이 크게 늘어난다. 추가로 성능을 더욱 향상시키기 위해 LDPC 부호 기반의 터보 등화 방법을 사용한다. 이 시스템의 경우 반복횟수의 증가로 계산량이 매우 크게 증가하는 단점이 있다. 이러한 계산량의 증가를 보완하기 위하여 LDPC 부호와 연판정 이후의 신호를 이용하여 적응 등화기를 조절한다. 시뮬레이션 결과 더 적은 계산량으로 LDPC 부호를 사용하고 SISO-MMSE(soft input soft output minimum mean square error)알고리즘 기반인 터보 등화기에 근접하는 성능을 내는 것을 확인하였다.

Lattice Reduction-Based Approximate MAP Detection with Bit-Wise Combining and Integer Perturbed List Generation

For iterative detection and decoding (IDD) in multiple-input multiple-output (MIMO) systems, the log-likelihood ratio (LLR) of each coded bit can be found by an optimal bit-wise maximum a posteriori probability (MAP) detector. However, since this MAP detector requires a prohibitively high computational complexity, low-complexity suboptimal detectors are desirable. In this paper, lattice reduction (LR)-based MIMO detection is investigated to derive a low-complexity detector that can achieve near MAP performance for IDD. In order to approximate LLR values incorporating the extrinsic information provided by a soft-input soft-output (SISO) decoder, bit-wise LR-based minimum mean square error (MMSE) filters are derived. Furthermore, in order to minimize the performance degradation due to quantization (or rounding) errors in the LR-based detection, a low-complexity integer perturbed list generation method is proposed, where no tree search is used by taking advantage of a near orthogonal channel basis obtained by LR. Through a complexity analysis and simulations, it is shown that the proposed approach achieves near optimal performance, while the complexity is comparable with that of the MMSE soft cancellation method, which is known to be computationally efficient. As a bit-wise detector, a parallel implementation of the proposed method would be straightforward, which lowers the detection delay.

Distributed Soft Coding with a Soft Input Soft Output (SISO) Relay Encoder in Parallel Relay Channels

In this paper, we propose a new distributed coding structure with a soft input soft output (SISO) relay encoder for error-prone parallel relay channels. We refer to it as the distributed soft coding (DISC). In the proposed scheme, each relay first uses the received noisy signals to calculate the soft bit estimate (SBE) of the source symbols. A simple SISO encoder is developed to encode the SBEs of source symbols based on a constituent code generator matrix. The SISO encoder outputs at different relays are then forwarded to the destination and form a distributed codeword. The performance of the proposed scheme is analyzed. It is shown that its performance is determined by the generator sequence weight (GSW) of the relay constituent codes, where the GSW of a constituent code is defined as the number of ones in its generator sequence. A new coding design criterion for optimally assigning the constituent codes to all the relays is proposed based on the analysis. Results show that the proposed DISC can effectively circumvent the error propagation due to the decoding errors in the conventional detect and forward (DF) with relay re-encoding and bring considerable coding gains, compared to the conventional soft information relaying.

Lattice Reduction-Based MIMO Iterative Receiver Using Randomized Sampling

For iterative detection and decoding (IDD) in multiple-input multiple-output (MIMO) systems, although the maximum a posteriori probability (MAP) detector is desirable in terms of performance, it is difficult to be employed due to its prohibitively high complexity as an exhaustive search is used. In this paper, a lattice reduction (LR)-based MIMO detection method is studied to achieve near MAP performance with reasonably low complexity for IDD. The a priori information (API), which is available from a soft-input soft-output (SISO) decoder, is taken into account to generate a list with a randomized successive interference cancellation (SIC) method. More specifically, a joint Gaussian distribution is used to convert the API into the LR domain and a modified sampling distribution, which was originally adopted for near optimal LR-based detection in non-IDD MIMO systems, is derived for random sampling to build a list of candidate vectors of high a posteriori probability (APP) with low complexity. It is shown that the IDD receiver with the proposed method outperforms those with the conventional LR-based methods, where no API is taken into account to build a list. Furthermore, the trade-off between performance and complexity is exploited with varying list length.

A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes

This paper highlights the implementation challenges faced by the current high performing error resilient joint source channel coding (JSCC) techniques based on the concept of soft-input soft-output (SISO) decoding of arithmetic codes (AC). Further, it proposes several efficient algorithmic and a very large scale integration (VLSI) architectural techniques to improve the throughput performance of SISO for JSCC. The VLSI hardware implementation of the proposed algorithm, when implemented on a 90 nm standard cells technology running at 588 MHz, achieves a decoding throughput of up to 2.63 Mbits/s capable of decoding QCIF format for video conferencing.

Performance Enhancement of SOVA Based Decoder in SCCC and PCCC Schemes

This study proposes a simple scaling factor approach to improve the performance of parallel-concatenated convolutional code (PCCC) and serial concatenated convolutional code (SCCC) systems based on suboptimal soft-input soft-output (SISO) decoders. Fixed and adaptive scaling factors were estimated to mitigate both the optimistic nature of a posteriori information and the correlation between intrinsic and extrinsic information produced by soft-output Viterbi (SOVA) decoders. The scaling factors could be computed off-line to reduce processing time and implementation complexity. The simulation results show a significant improvement in terms of bit-error rate (BER) over additive white Gaussian noise and Rayleigh fading channel. The convergence properties of the suggested iterative scheme are assessed using the extrinsic information transfer (EXIT) chart analysis technique.

VLSI Architecture for MIMO Soft-Input Soft-Output Sphere Detection

Achieving good detection performance while incurring low complexity is known to be one of the major challenges in multiple-input multiple-output (MIMO) communications based on spatial multiplexing. The tuple search detector (TSD) was recently introduced, improving this trade-off with regard to other tree-search-based algorithms (e.g. single tree search or list sphere detector). Motivated by the tremendous gain achievable through the turbo principle and based on a previously developed soft-output (SO) TSD implementation, this work presents the first soft-input soft-output (SISO) TSD realization, scalable in constellation size and number of antennas and mapped to a highly parallel and pipelined VLSI architecture. The proposed SISO-TSD VLSI realization is instantiated for 4 × 4 MIMO transmission and 64-QAM constellation in 65-nm CMOS technology. For a given BER?complexity trade-off, the throughput ranges from 57.3 Mbps (iterative detection-decoding with 3 iterations) to 403.6 Mbps (non-iterative detection-decoding) at a clock frequency of 454 MHz. The BER?complexity trade-off can be moreover adjusted according to transmission conditions, reaching >1 Gbps in high SNR scenarios. A silicon area of 0.14 mm2 (97.7 kGEs) is occupied by the SISO-TSD core, reporting low power dissipation (58.2 mW --- 73.9 mW) under typical case operating conditions. The proposed detector implementation achieves hence high throughput with reasonable hardware complexity, representing a very competitive strategy with regard to relevant state-of-the-art realizations.