Soft Errors In Logic Circuits Research Articles

Transistor Sizing in Order to Hardening CMOS circuit against Soft Error

to the shrinking of feature size and reduction in supply voltages, nano scale circuits have become more susceptible to radiation induced transient faults. Transient faults caused by radiation are becoming a major barrier to robust system design manufactured at technology nodes like 90nm, 65nm or smaller. A single event upset (SEU) may cause a bit flips in some latches or memory elements, thereby altering the state of the system, leading to a soft error. Soft errors in memory have traditionally been a much greater concern than soft errors in logic circuits. In this paper we propose an accurate and prompt approach in order to finding minimum transistor size to hardening CMOS circuits against SEU. One of the hardening CMOS circuit methods against SEU is transistor sizing; a large transistor can dissipate the injected charge as quickly as it is deposited so that the transient does not achieve sufficient magnitude and duration to propagate to gates in fan out. Most hardening methods based on transistor sizing have high area overhead. Since the suggested method at this paper is obtained minimum transistor size for hardening, the optimization of area will be done. experimental results show that present mathematical model results are agree well with SPICE simulations, while allowing for very fast analysis.

Robust Flip-Flop Circuit against Soft Errors for Combinational and Sequential Logic Circuits

Soft errors in logic circuits are a significant problem in LSIs. We need to consider two phenomena in logic circuits, single-event-upsets (SEUs) which are soft errors in sequential elements, and single-event-transients (SETs) which are soft errors in combinational logic. In this study, we have proposed a robust flip-flop circuit for protecting against SET and SEU problems. This flip-flop mitigates SETs by a low pass filter using a C-element with a delay element. The flip-flop also mitigates SEUs by a multi node latch technique. SEU mitigation efficiencies of the flip-flop are estimated by accelerated alpha particle and neutron experiments. SET mitigation efficiencies of the flip-flop are estimated by simulation. The flip-flop can protect against 99.8% of SEU and 85% of SET with low penalties.

Neutron-Induced Soft-Error Simulation Technology for Logic Circuits

In this paper, we describe the simulation technology used to estimate soft errors in logic circuits. The neutron induced soft-error simulator (NISES), which was previously developed for estimating soft-errors in memories is applied to the estimating soft errors in latch circuits and its effectiveness is shown. We model soft-error phenomena in combinational circuits and develop a novel simulation system for estimating soft errors in such circuits. Estimated results show that soft-error rate increases in combinational circuits as technology advances. Soft errors in logic circuits will thus become crucial.