Soft Error Rate Measurements Research Articles

Energy-Resolved Soft-Error Rate Measurements for 1–800 MeV Neutrons by the Time-of-Flight Technique at LANSCE

Problems caused by neutron-induced soft errors in electrical devices are becoming increasingly common in various applications. The neutron-energy-dependent soft-error rate is indispensable for evaluating the frequency of such errors in different neutron fields. We have observed the energy-dependent neutron-induced error rates continuously over the energy range of 1–800 MeV at Los Alamos Neutron Science Center (LANSCE). This was made possible by using extremely fast circuits built into field-programmable gate arrays (FPGAs) for time-of-flight measurement. Current experimental results revealed the overall trend of the error rate, which gradually increases up to 20 MeV. Interestingly, the rate depended on the type of device, and the errors occurred even below the threshold energy of the nuclear cross section of silicon, 2.75 MeV.

Multi-Poisson process analysis of real-time soft-error rate measurements in bulk 65 nm and 40 nm SRAMs

Altitude and underground real-time soft error rate (SER) measurements on SRAM circuits have been analyzed in terms of independent multi-Poisson processes describing the occurrence of single events as a function of bit flip multiplicity. Applied for both neutron-induced and alpha particle-induced SERs, this detailed analysis highlights the respective contributions of atmospheric radiation and alpha contamination to multiple cell upset mechanisms. It also offers a simple way to predict by simulation the radiation response of a given technology for any terrestrial position, as illustrated here for bulk 65nm and 40nm SRAMs.

Real-time soft error rate measurements on bulk 40 nm SRAM memories: a five-year dual-site experiment

This paper reports five years of real-time soft error rate experimentation conducted with the same setup at mountain altitude for three years and then at sea level for two years. More than 7 Gbit of SRAM memories manufactured in CMOS bulk 40 nm technology have been subjected to the natural radiation background. The intensity of the atmospheric neutron flux has been continuously measured on site during these experiments using dedicated neutron monitors. As the result, the neutron and alpha component of the soft error rate (SER) have been very accurately extracted from these measurements, refining the first SER estimations performed in 2012 for this SRAM technology. Data obtained at sea level evidence, for the first time, a possible correlation between the neutron flux changes induced by the daily atmospheric pressure variations and the measured SER. Finally, all of the experimental data are compared with results obtained from accelerated tests and numerical simulation.

Real-time soft-error rate measurements: A review

The real-time (or life testing) soft-error rate (SER) measurement is an experimental reliability technique to determine the soft error sensitivity of a given component, circuit or system from the monitoring of a population of devices subjected to natural radiation and operating under nominal conditions. This review gives a survey over recent real-time SER experiments, conducted in altitude and/or underground, and investigating modern CMOS logic technologies, down to the 40nm technological node. The review also includes our different contributions conducted during the last decade on the ASTEP Platform (Altitude Single Event Effects Test European Platform) and at the LSM facility (Underground Laboratory of Modane) to characterize soft error mechanisms in advanced static (SRAM) memories. Finally, the review discusses the specific advantages and limitations of this approach as well as its comparison with accelerated tests using intense particle beams or sources.

Thermal neutron induced soft error rate measurement in semiconductor memories and circuits

Soft error rate (SER) testing and measurements of semiconductor circuits with different operating voltages and operating conditions have been performed using the thermal neutron beam at the Radiation Science and Engineering Center (RSEC) at Penn State University. The high neutron flux allows for accelerated testing for SER by increasing reaction rate densities inside the tested device that gives more precision in the experimental data with lower experimental run time. The effect of different operating voltages and operating conditions on INTEL PXA270 processor has been experimentally determined. Experimental results showed that the main failure mechanism was the segmentation faults in the system. Failure response of the system to the operating conditions was in agreement with the general behavior of SERs.

Neutron-induced soft error rate measurements in semiconductor memories

Soft error rate (SER) testing of devices have been performed using the neutron beam at the Radiation Science and Engineering Center at Penn State University. The soft error susceptibility for different memory chips working at different technology nodes and operating voltages is determined. The effect of 10B on SER as an in situ excess charge source is observed. The effect of higher-energy neutrons on circuit operation will be published later. Penn State Breazeale Nuclear Reactor was used as the neutron source in the experiments. The high neutron flux allows for accelerated testing of the SER phenomenon. The experiments and analyses have been performed only on soft errors due to thermal neutrons. Various memory chips manufactured by different vendors were tested at various supply voltages and reactor power levels. The effect of 10B reaction caused by thermal neutron absorption on SER is discussed.

Twisted bit-line technique for multi-gigabit DRAMs

A new twisted bit-line (TBL) technique is presented to reduce bit-line coupling noise for multi-gigabit DRAMs. Sufficient noise reduction effects have been monitored through soft-error rate measurement on test chips using the proposed TBL technique. Also, the problem of excessive chip area penalty in the conventional TBL techniques can be solved in the proposed TBL technique.

Laminated media for high-density recording

The magnetic recording properties of laminated media structures on hard disks are discussed, including an overview of work on this topic. The primary performance advantage of laminated media is a significant reduction in media noise. The various mechanisms proposed for this noise reduction are considered. Other issues discussed include the optimal properties for the nonmagnetic interlayers, the influence of lamination on bulk magnetic properties, soft error rate measurements, and process challenges. The most important mechanism for the improved performance that has been obtained is decoupling of the noise sources in the various layers. The optimum interlayer thickness is in the range of 20-50 AA and seems to depend on the sputtering system and process conditions used. >