Soft Error Cross Section Research Articles

Evaluating Fault-Tolerant Techniques on COTS RISC-V NOEL-V Processor in Zynq UltraScale+ FPGA Under Proton Testing

This work evaluates different fault tolerance techniques on the RISC-V NOEL-V processor synthesized into the SRAM-based Zynq UltraScale+ FPGA under proton testing. We investigate the effect of the cache size on the reliability of the processor and the use of scrubbing combined with triplication, duplication with comparison, and cache refreshing. The design area in SRAM-based FPGAs directly affects the soft error cross section. However, results show that increasing the L1 cache size and using the correct combination of mitigation techniques reduces the overall SEE susceptibility of the RISC-V NOEL-V processor.

Quantitative Research on Generalized Linear Modeling of SEU and Test Programs Based on Small Sample Data

Complex integrated circuits (ICs) have complex functions and various working modes, which have many factors affecting the performance of a single event effect. The single event effect performance of complex ICs is highly program-dependent and the single event sensitivity of a typical operating mode is generally used to represent the single event performance of the circuits. Traditional evaluation methods fail to consider the cross effects of multiple factors and the comprehensive effects of each factor on the single event soft error cross section. In order to solve this problem, a new quantitative study method of single event error cross section based on a generalized linear model for different test programs is proposed. The laser test data is divided into two groups: a training set and a validation set. The former is used for model construction and parameter estimation based on five methods, such as the generalized linear model and Ensemble, while the latter is used for quantitative evaluation and validation of a single event soft error cross section of the model. In terms of percentage error, the minimum mean estimation error on the validation set is 13.93%. Therefore, it has a high accuracy to evaluate the single event soft error cross section of circuits under different testing programs based on the generalized linear model, which provides a new idea for the evaluation of a single event effect on complex ICs.

Effects of Total-Ionizing-Dose Irradiation on SEU- and SET-Induced Soft Errors in Bulk 40-nm Sequential Circuits

Synergetic effects of total-ionizing-dose irradiation on the single event upset (SEU) and single event transient (SET) performance of 40-nm sequential circuits are studied at doses up to 2 Mrad(SiO2). The impacts of input pattern and supply voltage are evaluated. An initial increase of SEU- and SET-induced soft error cross-section versus total dose is observed, followed by a decreasing trend at higher doses. The maximum increase of SEU- and SET-induced soft error cross-section occurs when the total-ionizing-dose is approximately 1.5 Mrad(SiO2) in the studied sequential circuit. The SET-induced soft error cross-section versus total dose increases at a faster speed than the SEU-induced soft error cross-section.

Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs

This paper studies the implementation of Double Error Correction Orthogonal Latin Squares (OLS) in Xilinx Field Programmable Gate Arrays (FPGAs). Several existing options to implement the decoder are considered and evaluated. The results show that the decoder complexity can be significantly optimized by appropriately selecting the implementation that is better suited to the internal FPGA structure. A new implementation tailored for the FPGA structure is proposed, which has a more efficient physical resource utilization compared with the existing ones. It is shown that the improvement on resource utilization is also highly correlated with the soft error vulnerability. The proposed decoder scheme has a reduced soft error cross section compared with other implementations. Based on these results, it seems that optimizing the ECC implementation for FPGAs can be effective and may be useful for other codes.

Transport Characteristics of Secondary Charged Particles Resulting from High Energy Neutron in Silicon

Silicon is always the dominant semiconductor material of the modern semiconductor industry. This is as silicon can retain its semiconductor characteristics even at a higher temperature while the other semiconductor materials can't. However, when a silicon device is exposed to a flux of energetic radiation or particles, the effects from the radiation and the induced secondary particles can cause several degradation of the device performance. For the purpose of investigate the resultant effects from the bombardment of neutrons and the behavior of secondary charged particles in the silicon model, the neutron displacement defect was measured in situ and then followed by the simulation based on Monte Carlo method. The bombardment of neutron in the silicon model produce at least three secondary particles, which are alpha ˸α˹ particles, proton (p) particles and silicon recoil atoms, through the reactions of ˸̾˼α˹˼˰˸̾˼̀˹˰and neutron scattering respectively. The kinetic energy and range of these charged particles are different among themselves, and thus the probability of hitting and degradation effects in the silicon materials are varies. The simulation calculation showed that ˸̾˼α˹˰reaction induced soft error cross section of about 8.7 x 10-14 cm2 and for recoil atoms, it is about 2.9 x 10-15 cm2. There was no error of the silicon device configuration induced by proton particles until 1010 n/cm2.neutron fluence. It can be concluded that the largest portion of error in the silicon model is induced by the secondary alpha ˸α˹ particles.

Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors

With the emphasis on low-power design, achieving soft error reliability in combinational logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate combinational logic soft errors. This work shows that for certain circuits, reduction in both power and combinational logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits.

Theoretical Correlation of Broad Spectrum Neutron Sources for Accelerated Soft Error Testing

Several broad spectrum, high energy neutron source facilities exist throughout the world for accelerated soft error testing. However, none accurately replicate the terrestrial neutron spectra across the range of 1 MeV to 1 GeV. The objective of this study is to quantify the errors introduced in accelerated soft error measurements from these facilities using a range of theoretical soft error cross-sections for both high and low critical charge events.

Neutron radiation effects on metal oxide semiconductor (MOS) devices

The main purpose of this study is to provide the knowledge and data on Deuterium–Tritium (D–T) fusion neutron induced damage in MOS devices. Silicon metal oxide semiconductor (MOS) devices are currently the cornerstone of the modern microelectronics industry. However, when a MOS device is exposed to a flux of energetic radiation or particles, the resulting effects from this radiation can cause several degradation of the device performance and of its operating life. The part of MOS structure (metal oxide semiconductor) most sensitive to neutron radiation is the oxide insulating layer (SiO2). When ionizing radiation passes through the oxide, the energy deposited creates electron–hole pairs. These electron–hole pairs have been seriously hazardous to the performance of these electronic components. The degradation of the current gain of the dual n-channel depletion mode MOS caused by neutron displacement defects, was measured using in situ method during neutron irradiation. The average degradation of the gain of the current is about 35mA, and the change in channel current gain increased proportionally with neutron fluence. The total fusion neutron displacement damage was found to be 4.8×10−21 dpa per n/cm2, while the average fraction of damage in the crystal of silicon was found to be 1.24×10−12. All the MOS devices tested were found to be controllable after neutron irradiation and no permanent damage was caused by neutron fluence irradiation below 1010n/cm2. The calculation results shows that (n,α) reaction induced soft-error cross-section about 8.7×10−14cm2, and for recoil atoms about 2.9×10−15cm2, respectively.

Implications of Dopant-Fluctuation-Induced $V_{\rm t}$ Variations on the Radiation Hardness of Deep Submicrometer CMOS SRAMs

Accurately analyzing the single-event (SE) vulnerability of static random-access memory (SRAM) cells leads to precisely calculated soft-error rates (SERs). Random dopant-fluctuation-induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> variations affect the SE vulnerability of these memory cells and increase the intercell spread in critical charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</sub> ), which cause SE upsets. This might consequently lead to higher SERs than would be calculated, assuming a single critical charge. Monte Carlo simulations in the IBM 130- and 90-nm technologies quantify this spread in Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</sub> and in SRAM soft-error cross sections with increasing variance. For a radiation-tolerant design, a statistical-design methodology must be used to validate existing hardening schemes and to obtain the expected tolerance levels.

Predicting Thermal Neutron-Induced Soft Errors in Static Memories Using TCAD and Physics-Based Monte Carlo Simulation Tools

A combination of commercial simulation tools and custom applications utilizing Geant4 physics libraries is used to analyze thermal neutron induced soft error rates in a commercial bulk CMOS SRAM. Detailed descriptions of the sensitive regions based upon technology in computer-aided design calibration are used in conjunction with a physics-based Monte Carlo simulator to predict neutron soft error cross sections that are in good agreement with experimental results

Simulation of nucleon-induced nuclear reactions in a simplified SRAM structure: scaling effects on SEU and MBU cross sections

Academic 128/spl times/128 bit structures are simulated to study soft error cross sections induced by high-energy nucleons (n/p) in SRAM memories. The distributions of secondary ions are obtained by the nuclear high energy transport code and analyzed in terms of energy deposited in the sensitive volume of each memory cell. Multiple-bit upset cross sections are compared to single-event upset cross sections, and trends associated with scaling effects are presented.

Evaluation of soft-error hardness of DRAMs under quasi-heavy ion irradiation using He single ion microprobe technique

Soft-error immunity of a 256 kbit DRAM against quasi-heavy ion irradiation has been evaluated using He single ion microprobe at Waseda University. The technique for hitting micron size area with arbitrary number of He ions enables us to simulate the space environment under irradiation of heavy ions with higher LET than that of /spl alpha/-particles. From the maps of error-sensitive sites obtained by irradiating various number of-He ions, the threshold LET of soft-errors, effect of diffused charges on the soft-error cross section, and susceptibility to multi-bit errors have been estimated. The results of measuring single-ion induced noise charges at the PN junction which is considered as equivalent to the storage node of the DRAM have been presented and the origins which determine the soft-error immunity under irradiation with various LET have been discussed.

Soft-Error on Memory ICs Induced by D-T Neutrons.

Abstract In order to examine the fusion neutron induced soft-error on memory ICs, several kinds of CMOS SRAM ICs were irradiated around room temperature with 14MeV neutrons from OKTAVIAN. The pattern and rate of soft-error upsets on the ICs were measured in situ during neutron irradiation. It was found that neutron reactions caused not multiple but single type soft-errors and the number of the soft-errors increased proportionally with neutron fluence. There was also a large difference in the soft-error upset rate between set (from 0 to 1) and reset (from 1 to 0) soft-errors for some kinds of ICs. Considering the cell population in a chip, we obtained the neutron susceptibility constant, i.e. bit soft-error cross section of 2–3× 1015 cm2 for 16 K and 64 K bit CMOS SRAM ICs, and 6–9×10-14cm2 for 256 K and 1 Mbit ICs, respectively. Also, all memory cells were controllable after neutron irradiation and no permanent damage was caused by neutron fluence irradiation below about 1012 n/cm2.

Track structure effects at p- n junctions in microelectronic circuits

Accurate predictions of the soft error rates in microelectronic circuits exposed to energetic charged particles require the ability to predict charge collection at a junction as a function of the LET of the traversing particle, and the ability to predict the response of the circuit to the resulting voltage swing across the junction. Detailed modeling of charge collection will require quantitative information on the distribution of charges about the particle trajectory as a function of time from the initiation of the track until the charge is collected across the junction. Track structure models may contribute to quantitative explanations of the shape of the dependence of the soft error cross section on LET and the frequency of multiple upset events in VLSI circuits.

Full temperature single event upset characterization of two microprocessor technologies

Data for the Fairchild 9450 I/sup 3/L bipolar microprocessor and the Harris 80C86 CMOS/epi (vintage 1985) microprocessor are presented, showing single-event soft errors for the full mil-spec temperature range of -55 degrees C to 125 degrees C. These data show for the first time that the soft-error cross sections continue to decrease with decreasing temperature at subzero temperatures. The temperature dependence of the two parts, however, is very different. >

Single Event Effects in High Density CMOS SRAMs

The effects of epi-substrate and a cell power supply layout on heavy-ion induced latch-up for 64K SRAMs are examined by heavy-ion exposure tests using a cyclotron. It is shown that epi-substrate alone is not sufficient to prevent latch-up. A cell power supply layout technique, that is, power is supplied through the well for MOSFETs in the well, combined with epi-substrate is very effective in preventing latch-up for high density CMOS/BULK memories. Soft error cross sections and threshold LETs for various CMOS SRAMs are determined by heavy-ion exposure tests. The threshold LET for conventional 64K SRAMs decreases to about one-fifth that of 1K SRAMs.

A 64K SRAM with high immunity from heavy ion induced latch-up

A 64-kbit SRAM with high latch-up immunity has been developed with the application of a well-source structure combined with an epi-substrate. Heavy-ion beam exposure tests reveal that the device has high immunity from cosmic-ray induced latch-up, and the soft-error cross section is about 8.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /(bit particle) for 73-MeV Ar ions.

Proton-Induced Nuclear Reactions in Silicon

Measurements of the energy deposited in silicon surface-barrier detectors as a result of proton-induced nuclear reactions were carried out at the Harvard Cyclotron for protons with incident energies ranging from 50 to 158 MeV and detectors with thicknesses of 2.5, 4.2, 24.1, 100, and 200 ?m. The number of events in which a given threshold amount of energy is deposited in a 4.2 ?m detector varied with incident proton energy in a manner similar to previous measurements of the proton-induced soft-error cross section. The number of events in which at least a threshold amount of energy was deposited in the detector fell off in a near exponential manner with increasing threshold energy. The data were found to be in reasonable agreement with a computer simulation model developed in our laboratory. The model is used to illustrate how the mass spectra of the residual nuclear fragments shifts towards lower masses with increasing recoil energy. Lighter recoils have longer ranges and a greater chance of leaving a microscopically thin sensitive volume element before coming to their end of range.

Soft Errors Induced by Energetic Protons

Two types of 4K dynamic RAM devices have been shown to exhibit soft errors when exposed to energetic protons. Considerable variation in sensitivity was found among devices, even those of the same model. For individual devices the soft error cross section increased with proton energy over the range of proton energies of from 18 to 130 MeV. The types of errors observed and their locations in memory were also found to depend on the beam energy.