Snapback Voltage Research Articles

Single-event burnout hardening of RC-IGBT with the raised N-buffer layer

This paper proposes a reverse conducting insulated gate bipolar transistors (RC-IGBT) structure with a raised N-buffer layer (RNB-IGBT) to improve the single-event burnout (SEB) robustness. The electrical and radiation properties of the structure were verified by TCAD simulations. At the same snapback voltage of 0.22 V and the liner energy transfer (LET) of 60 MeVcm2/mg conditions, the SEB threshold of RNB-IGBT is improved by 52 % compared to that of conventional RC-IGBT. This result indicates that the raised N-buffer layer of the RNB-IGBT can effectively reduce impact ionization, so it can suppress excessive heat concentration and avoid induce SEB.

On the Use of Acoustic Methods for the Detection of Electrostatic Capture of Diaphragm in Capacitive MEMS Microphones

Most mobile phones today have capacitive micro-electro-mechanical systems (MEMSs) microphones that use either single or dual diaphragms. Methods to detect failures easily and non-invasively have become of critical importance for microphones mobile phone manufacturers as a basis for built-in self-test (BIST) and self-repair (BISR) strategies. In that regard, a four-layer framework is presented that includes lumped element modeling (LEM), failure mode simulation, failure mode discrimination, and recovery. The frequency response of the microphone is taken as the main output to analyze. To experimentally validate this framework, this article provides a failure mode induction method based on bias voltage sweeping and four new techniques, based solely on acoustic measurements to discriminate the states of electrostatic capture for single diaphragm capacitive MEMS microphones. These include 1) analysis of an acoustic signature that is unique to electrostatic capture based on cosine similarity analysis; 2) −3 dB point measurement; 3) +3 dB point measurement; and 4) cluster analysis. Measurement of pull-in voltage and snapback voltage ranges is further demonstrated based on sensitivity measurements in laboratory conditions and response magnitude and noise power measurements in non-laboratory conditions. Up to 100% success rate in detecting electrostatic capture of diaphragm is reported for this type of device.

Switching Stability Analysis of Paralleled RC-IGBTs With Snapback Effect

In this article, a study of the snapback behavior of reverse conducting IGBTs (RC-IGBTs) by means of 2-D TCAD simulations is carried out. Half-cell TCAD models of 1200-V RC-IGBT structures with different snapback voltage levels were generated by varying the peak doping concentration of the punch-through N-buffer region. First observations show that snapback could be an issue for low current switching commutations of paralleled RC-IGBTs operating at low temperatures, where one device falls back into unipolar mode and current is completely misshared. Results show that the RC-IGBT snapback voltage level, circuit variations, and operating conditions play a critical role for determining whether the parallel RC-IGBTs operate in a stable or unstable mode.

New DDSCR structure with high holding voltage for robust ESD applications* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61774129, 61827812, and 61704145), the Huxiang High-level Talent Gathering Project from the Hunan Science and Technology Department, China (Grant No. 2019RS1037), and the Changsha Science and Technology Plan Key Projects, China (Grant Nos. kq1801035 and kq1703001).

A novel dual direction silicon-controlled rectifier (DDSCR) with an additional P-type doping and gate (APGDDSCR) is proposed and demonstrated. Compared with the conventional low-voltage trigger DDSCR (LVTDDSCR) that has positive and negative holding voltages of 13.371 V and 14.038 V, respectively, the new DDSCR has high positive and negative holding voltages of 18.781 V and 18.912 V in a single finger device, respectively, and it exhibits suitable enough positive and negative holding voltages of 14.60 V and 14.319 V in a four-finger device for ±12-V application. The failure current of APGDDSCR is almost the same as that of LVT-DDSCR in the single finger device, and the four-finger APGDDSCR can achieve positive and negative human-body model (HBM) protection capabilities of 22.281 kV and 23.45 kV, respectively, under 40-V voltage of core circuit failure, benefitting from the additional structure. The new structure can generate a snapback voltage on gate A to increase the current gain of the parasitic PNP in holding voltage. Thus, a sufficiently high holding voltage increased by the structure can ensure that a multi-finger device can also reach a sufficient holding voltage, it is equivalent to solving the non-uniform triggering problem of multi-finger device. The operating mechanism and the gate voltage are both discussed and verified in two-dimensional (2D) simulation and experiemnt.

A Dual-MOS-Triggered Silicon-Controlled Rectifier for High-Voltage ESD Protection

A dual-MOS-triggered silicon-controlled rectifier (DMTSCR) has been firstly developed for high-voltage (HV) electrostatic discharge (ESD) protection. Compared to the reported SCRs with modified structures, the DMTSCR harvests a series of advantages such as a high holding voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{h}$ </tex-math></inline-formula> ), a strong ESD robustness, and a low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t1}$ </tex-math></inline-formula> , thanks to its embedded structures including a gate-to-VDD PMOS, a gate-grounded NMOS, and a modified SCR. Thus, the DMTSCR has the largest figure of merit as high as 1.8 mA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}^{2}$ </tex-math></inline-formula> . By further optimizing the layout and the key spacing between the embedded PMOS and NMOS of DMTSCR, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{h}$ </tex-math></inline-formula> increased from 8.4 to 17.4 V, the turn-on resistance remarkably decreased to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.4~\Omega $ </tex-math></inline-formula> , and the turn-on voltage was clamped at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{h}$ </tex-math></inline-formula> . The optimized DMTSCR with a small chip area possesses an ESD robustness of 3000 V evaluated by the human body model. Meanwhile, the operation mechanism simulated by Sentaurus exhibited good agreements with the theoretical circuit analysis, and the simulated electrical characteristics were consistent with those measured from the experimental devices. The layout-optimized DMTSCR with good clamping ability and zero snapback voltage is a promising solution for stacking to meet various HV ESD protection requirements.

Snapback‐free reverse conducting IGBT with p‐float and n‐ring surrounding trench‐collector

A reverse conducting (RC) insulated gate bipolar transistor (IGBT) with p-float and n-ring surrounding trench-collector is proposed. The p-floats surrounding sidewalls of trench-collectors suppress snapback and also avoid snapback when there are semiconductor/trench-collector interface charges (Q f). The n-rings surrounding the top of the trench-collectors speed up the forward recovery and ensure a high breakdown voltage. Technology computer aided design (TCAD) simulations are carried out to compare the proposed RC-IGBT and the RC-IGBT with p-poly trench-collector (PTC RC-IGBT). With Q f = 1 × 1011 cm−2, the proposed RC-IGBT is snapback-free while the PTC RC-IGBT has a snapback voltage of 4.43 V. The peak forward recovery voltage of the proposed RC-IGBT (12 V) is much lower than that of the PTC RC-IGBT (246 V). Besides, the reverse recovery charge of the two RC-IGBTs is 48% lower than that of the PiN diode.

Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector–MTJ Cooptimization

To increase the density of magnetoresistive random access memory (MRAM) beyond the 1T1MTJ MRAM cell in use today, the design space for 1S1MTJ MRAM array is analyzed by cooptimizing both selectors and MTJs. Current low-resistance MTJs for 1T1MTJ MRAM are not suitable for 1S1MTJ MRAM. Threshold-type selectors would induce a strong read disturb on the MTJ due to the snapback voltage (VTH-VHOLD) when the selector is turned on. Also, exponential-typeselectors would degrade the read margin (RM) due to its large ON-state resistance. When using existing selectors to achieve a 1-M-bit 1S1MTJ array, it is necessary to adjust the product of resistance and area(RA) and the diameter of the MTJ. An MTJ with the RA = 15 Ω · μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the diameter = 50 nm can meet the criterion of RM > 10% for both exponential-type selectors (exponential slope = 300-500 mV/decade with the current density ~ 1 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and threshold-type selectors (VTH-VHOLD ~ 250 mV). A design space accommodating a selector variation of around 1% can be found for MTJs with tunnel magnetoresistance ratio (TMR) <; 250%. With an increased TMR of 250%-350% of the MTJ, the tolerance of variations for exponential-type selectors and threshold-type selectors can be improved to 2% and 4%, respectively. This provides a chance for the 1S1MTJ MRAM with existing selectors.

Large oscillation of electrostatically actuated curved beams

This paper investigates the responses of initially curved micro-beams subjected to an electrostatic excitation. A Euler–Bernoulli beam theory is utilized to derive the governing equation of motion. A reduced-order model was developed by discretizing the equation of motion using straight beam mode shapes as basis functions in a Galerkin expansion. The results show evidence of the superharmonic resonances of order-three and two in addition to primary resonance. The co-existence of multiple stable orbits observed around only one stable equilibrium and under excitation waveforms with RMS voltage less than the snap-back voltage. These branches are a branch of small orbits within a narrow potential well and two branches of medium-sized and large orbits within a wider potential well. The transition between them results in the characteristic of the double peaks appearing in the frequency-response curve. We also report a bubble structure along the medium-sized branch consists of a cascade of period-doubling bifurcations and a cascade of reverse period-doubling bifurcations. A chaotic attractor develops within that structure at larger excitation levels. It demonstrates evidence of chaos with a wide-based spectrum and an elevated noise-floor. Odd-periodic windows appear also within the attractor including period-three (P-3), period-five (P-5) and period-six (P-6) windows. The chaotic attractor terminates in a cascade of reverse period-doubling bifurcations of period-four (P-4) orbits and period-two (P-2) orbits.

Simulation Study of a Novel Snapback Free Reverse-Conducting SOI-LIGBT With Embedded P-Type Schottky Barrier Diode

In this article, a novel reverse-conducting lateral insulated gate bipolar transistor (RC-LIGBT) with embedded diode and p-type Schottky Barrier Diode (p-SBD) is proposed. The two diodes are connected in series through a floating electrode, which provides a current path for carriers in reverse-conducting mode. Compared with the Separated Shorted-Anode RCLIGBT (SSA-RC-LIGBT), the proposed structure not only eliminates the snapback voltage ( $\Delta {V}_{\text {SB}}$ ) but also avoids the waste of device area. Therefore, the superior reverse recovery characteristics and excellent tradeoff relationship between ON-state voltage ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ) are obtained. The reverse recovery charge of the proposed RC-LIGBT shows 43.9% and 63.2% reduction compared with those of the SSA-RC-LIGBT with ${L}_{\text {B}}$ (distance between the p+ collector and the shorted n+ collector) being 34 and $64~\mu \text{m}$ , respectively. The turn-off loss of the proposed RC-LIGBT at ${V}_{ \mathrm{\scriptscriptstyle ON}} = {2.6}$ V is reduced by 68.2% and 87.1% compared with those of the SSA-RC-LIGBT with $\sf \Delta {V}_{\text {SB}} = {0.48}$ V and $\sf \Delta {V}_{\text {SB}} = {0.17}$ V, respectively. Moreover, the proposed RC-LIGBT has a self-adjusted collector injection efficiency under different temperatures to dramatically improve the Short Circuit Safe Operation Area (SCSOA).

Gate Current and Snapback of 4H-SiC Thyristors on N+ Substrate for Power-Switching Applications

High-power switching applications, such as thyristor valves in a high-voltage direct current converter, can use 4H-SiC. The numerical simulation of the 4H-SiC devices requires specialized models and parameters. Here, we present a numerical simulation of the 4H-SiC thyristor on an N+ substrate gate current during the turn-on process. The base-emitter current of the PNP bipolar junction transistor (BJT) flow by adjusting the gate potential. This current eventually activated a regenerative action of the thyristor. The increase of the gate current from P+ anode to N+ gate also decreased the snapback voltage and forward voltage drop (Vf). When the doping concentration of the P-drift region increased, Vf decreased due to the reduced resistance of a low P-drift doping. An increase in the P buffer doping concentration increased Vf owing to enhanced recombination at the base of the NPN BJT. There is a tradeoff between the breakdown voltage and forward characteristics. The breakdown voltage is increased with a decrease in concentration, and an increase in drift layer thickness occurs due to the extended depletion region and reduced peak electric field.

VO2 Switch for Electrostatic Discharge Protection

On-chip protection from electrostatic discharge (ESD) and electrical overstress (EOS) is a continuous challenge in the semiconductor industry, requiring significant design costs and die space. Insulator-metal transition (IMT) materials like vanadium dioxide (VO2) could be used as bidirectional, compact voltage snapback devices for ESD protection that are not required to be in the front-end silicon. However, the reliability and response of these materials to ESD is not yet well studied. Here, we perform transmission line pulse (TLP) tests on thin film (50– 150 nm) VO2 devices. These can repeatedly sustain high currents in their metallic state, but still return to insulating once an ESD event is over. Devices with widths from 5 to 50 $\mu \text{m}$ can carry a maximum current ( ${I} _{{\text {t}2}}$ ) from ~1 to over 10 A, equivalent to ~1 to 15 kV of ESD protection. Furthermore, the snapback voltage can be engineered by varying the device length. These results suggest that IMT materials could be promising for use in on-chip ESD/EOS protection.

Electrostatic arch micro-tweezers

This paper presents a novel electrostatic micro-tweezers to manipulate particles with diameters up to 14 μm. The tweezers consist of two grip-arms mounted to an electrostatically actuated initially curved micro-beam. It exploits bistable equilibria, resulting from a snap-through instability, to close the separation distance between the two arms allowing them to grasp a large range of objects. The tweezers offer further control beyond the snap-through point, via electrostatic actuation, to increase pressure on larger objects or grasp smaller objects. The tweezers are fabricated in a p-type Silicon on Insulator (SOI) wafer. Euler-Bernoulli beam theory is utilized to derive the governing equation of motion taking into account the arms' rotary inertia and the electrostatic fringing field. A reduced-order model (ROM) is developed utilizing two, three and five symmetric modes in a Galerkin expansion. A finite element model (FEM) is also developed to validate the ROM and to study the arm tips' separation as a function of actuation voltage. The five-mode ROM is found to be convergent and accurate except in the vicinity of the snap-through saddle-node bifurcation. Our analysis shows that the tweezers can manipulate micro-particles with diameters ranging from 5 to 12μm with an operating voltage range limited by the snap-back voltage 100.2V and the pull-in voltage 153.2V.

Analysis of the Fast-Switching LIGBT With Double Gates and Integrated Schottky Barrier Diode

A novel fast-switching lateral-insulated gate bipolar transistor (LIGBT) with double gates and integrated Schottky barrier diode (SBD) is proposed and studied in this paper by TCAD simulation. In order to reduce the turn-off time and maintain a low forward voltage drop, the proposed structure introduces an integrated SBD structure at the anode and an additional trench gate at the cathode. First, the integrated SBD provides an extra electron extraction path and the additional trench gate enhances the injection of the N+-cathode. Furthermore, the insulated oxide pillar between the N-buffer and integrated SBD further reduces the snapback voltage. Finally, the simulation results show that the turn-off time of the conventional LIGBT is 52.4% larger than that of trench/planar gate SBD (TP-SBD) LIGBT under the same forward voltage of 1.49 V. Moreover, the latch current density of TP-SBD LIGBT is increased by nearly 200% compared to that of the conventional LIGBT, while almost the same latch voltage is obtained, so the proposed TP-SBD LIGBT can improve the latch immunity.

Design of a Gate Diode Triggered SCR for Dual-Direction High-Voltage ESD Protection

A novel gate diode triggered silicon-controlled rectifier (GDTSCR) with dual-direction high-voltage (HV) electrostatic discharge (ESD) protection and a low snap-back voltage is proposed and investigated. Compared to conventional MOS triggered SCR (MTSCR), the GDTSCR has two gate diodes and one additional n-p-n. Superior to the MTSCR, the GDTSCR exhibits a high holding voltage of 15 V, a small trigger voltage of 17 V, and a strong ESD robustness of 6000 V in an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1600~\mu \text{m}^{\textsf {2}}$ </tex-math></inline-formula> , benefitting from the gate-controlled field effect diodes and the weakened regenerative feedback of the SCR. As such, the proposed GDTSCR is an attractive device for constructing effective and latch-up immune solutions for HV ESD protection.

SOI-LDMOS Transistors With Optimized Partial n+ Buried Layer for Improved Performance in Power Amplifier Applications

In this paper, for the first time, we demonstrate the improvement in power capability and safe operating area of silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors for power amplifier applications by the introduction of a partial n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> buried layer (PNBL). The power capability of a transistor can be evaluated by P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> /A, which is the maximum power per unit area that can be delivered by the transistor and is an important parameter for power amplifiers. P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> is dependent on the snapback voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sb,QS</sub> ), OFF-state breakdown voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bd,OFF</sub> ), and maximum current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) in the quasi-saturation regime of an LDMOS transistor. Increase of P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> /A by the introduction of a PNBL in the SOI-LDMOS transistors is reported in this paper. The effects of variation of the length, thickness, and doping concentration of the PNBL on V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sb,QS</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> /A are analyzed in detail. It is shown that by optimizing the doping and length of the PNBL layer, the maximum power output from the transistor can be made significantly higher than that of a conventional device without PNBL. A procedure to design the optimized structure is also presented.

Analysis of the novel Snapback-Free LIGBT with fast-switching and improved latch-up immunity by TCAD Simulation

In this letter, a novel snapback-free LIGBT with fast-switching and improved latch-up immunity is proposed and investigated by TCAD simulation. The structure features a shorted-anode NPN (SA NPN) beside the insulated oxide trench in the N-buffer and a lowly doped P-region (PD) alongside the deep-oxide trench (DOT) in the N-drift. The SA NPN provides an effective path of electron extraction and completely suppresses the snapback voltage. The PD changes the transmission path of hole current, makes the distribution of hole current more uniform, and contributes to the depletion of the drift region. As simulation results show, at the same forward voltage drop of 1.40 V, the turn-off time for the proposed SAPD LIGBT is reduced by 36.6% and 57.4%, respectively, compared with SA LIGBT and DOT LIGBT. In addition, compared with DOT LIGBT, breakdown voltage is increased by 7.6% and latch-up voltage is increased by nearly 20% for the proposed SAPD LIGBT.

Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors

In this paper, for the first time, we report a nonmonotonic dependence of the snapback voltage ( $V_{\text {sb}}$ ) on the buried oxide thickness ( $t_{\text {BOX}}$ ) in silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors. Step-by-step analysis of this effect is carried out by decoupling the self-heating and impact-ionization effects that cause the turning ON of the parasitic bipolar junction transistor (BJT) and subsequently the snapback effect. It is observed that for LDMOS transistors with low $t_{\text {BOX}}$ , $V_{\text {sb}}$ increases with increase in $t_{\text {BOX}}$ due to reduction in drain current density as well as reduced impact ionization at higher lattice temperature. On the other hand, for high $t_{\text {BOX}}$ , $V_{\text {sb}}$ reduces with the increase in $t_{\text {BOX}}$ due to early switching ON of the parasitic BJT at higher temperature. Therefore, it is possible to find an optimum value of $t_{\text {BOX}}$ to obtain the highest $V_{\text {sb}}$ for an SOI-LDMOS transistor. An interesting observation is that with proper choice of $t_{\text {BOX}}$ , the safe operating area in SOI-LDMOS can be more than that of the corresponding bulk-LDMOS. A physics-based compact model is developed and implemented in Verilog-A. When compared with the Technology Computer Aided Design simulated results, our model exhibits high level of accuracy.

Electrical Characteristic Study of an SOI-LIGBT With Segmented Trenches in the Anode Region

This paper presents the electrical characteristic of a 500 V silicon-on-insulator (SOI) lateral insulated-gate bipolar transistor (LIGBT) with segmented trenches in the anode (STA) region. The STA-LIGBT features segmented n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> anodes and segmented trenches. The segmented n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> anodes are shorted to the p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> anode, which accelerates the extraction of stored electrons during the device turn-OFF. The segmented trenches are arranged between the p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> anode and the shorted n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> anode. The resistors between the adjacent segmented trenches and the adjacent segmented n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> anodes contribute to low snapback voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> ) while maintain high current density. In addition, an internal diode is formed by introducing the shorted n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> anode. The 3-D simulations and the experiments are carried out to characterize the electrical performances of the STA-LIGBT and its internal diode. Compared with the conventional SOI-LIGBT, the STA device achieves a 73% improvement in turn-OFF time (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) at the same current density. Correspondingly, the internal diode of the STA-LIGBT achieves a forward voltage drop (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> ) of 1.32 V and a reverse recovery time (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rr</sub> ) of 321 ns, which are superior to those of a conventional p-i-n SOI diode.

Reverse conducting–IGBTs initial snapback phenomenon and its analytical modelling

Analytical models have been proposed to describe the onset current density for the initial snapback in the transistor on-state mode and in the blocking state of reverse conducting-insulated gate bipolar transistors (RC-IGBT) for the stripe and cylindrical designs of the anode shorts. In cylindrical case, there are two possible ways in designing the anode shorts and the authors have proposed an analytical model for each of them. The considered RC-IGBTs are vertical with soft punch-through type buffer designs. The analytical model has been evaluated with the aid of 2-D device simulations and measurements. The authors have investigated the initial snapback phenomenon for different voltage class devices at a given technology (anode and buffer profiles) and found out that the snapback voltage increases with the blocking capability but not the snapback current density. The authors have also observed that the initial snapback phenomenon is more pronounced at lower temperatures. From the analytical model as well as simulation and measurement results, the authors have found that for a given voltage class and technology, the p + -anode width is the only remaining design degree of freedom which determines the initial snapback. The adjustment of the on-state losses can then be done with the proportion of the n + -short region.

ESD robustness studies on the double snapback characteristics of an LDMOS with an embedded SCR

Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis. According to this criterion, three typical structures are compared by numerical simulation and structural parameters which influence the second snapback are also analyzed to optimize the ESD characteristics. Experimental data showed that, as the second snapback voltage decreased from 25.4 to 8.1 V, the discharge ability of the optimized structure increased from 0.57 to 3.1 A.