Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors

Abstract

In this paper, for the first time, we report a nonmonotonic dependence of the snapback voltage ( $V_{\text {sb}}$ ) on the buried oxide thickness ( $t_{\text {BOX}}$ ) in silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors. Step-by-step analysis of this effect is carried out by decoupling the self-heating and impact-ionization effects that cause the turning ON of the parasitic bipolar junction transistor (BJT) and subsequently the snapback effect. It is observed that for LDMOS transistors with low $t_{\text {BOX}}$ , $V_{\text {sb}}$ increases with increase in $t_{\text {BOX}}$ due to reduction in drain current density as well as reduced impact ionization at higher lattice temperature. On the other hand, for high $t_{\text {BOX}}$ , $V_{\text {sb}}$ reduces with the increase in $t_{\text {BOX}}$ due to early switching ON of the parasitic BJT at higher temperature. Therefore, it is possible to find an optimum value of $t_{\text {BOX}}$ to obtain the highest $V_{\text {sb}}$ for an SOI-LDMOS transistor. An interesting observation is that with proper choice of $t_{\text {BOX}}$ , the safe operating area in SOI-LDMOS can be more than that of the corresponding bulk-LDMOS. A physics-based compact model is developed and implemented in Verilog-A. When compared with the Technology Computer Aided Design simulated results, our model exhibits high level of accuracy.