Small-signal Equivalent Circuit Parameters Research Articles

Impact of Graded AlGaN Buffer Layer Thickness on the DC, RF, Linearity, Intermodulation and Off-State Breakdown Characteristics of AlGaN Channel HEMT

This study examines the extraction of small-signal equivalent circuit parameters, linearity and intermodulation metrics, and capacitance–voltage characteristics for both AlGaN and GaN channel HEMTs. Compared to GaN channel HEMTs, AlGaN channel HEMTs have better linearity and intermodulation distortion. In the instance of AlGaN channel HEMTs, the device parasitics are decreased. Additionally, the effect of graded AlGaN buffer layer thickness on breakdown characteristics and linearity is examined. For breakdown characteristics, the 200 nm-graded AlGaN buffer layer thickness yields superior results with VBOff 157 V for a thickness of 200 nm (147 V in the case of 500 nm). At 200 nm thickness, the linearity and intermodulation distortion FOMs are also reasonably good, and the remaining device properties are essentially unchanged. Hence, the graded AlGaN buffer thickness can be reduced for high-voltage applications. For higher-voltage applications, the graded AlGaN buffer thickness can, therefore, be decreased.

Elimination of the Low Resistivity of Si Substrates in GaN HEMTs by Introducing a SiC Intermediate and a Thick Nitride Layer

We report the effect of a thick nitride layer on the high-frequency performance of AlGaN/GaN highelectron-mobility transistors (HEMTs) grown by metal oxide chemical vapor deposition (MOCVD) on a 6-inch Czochralski (Cz)-Si substrate. The thick nitride layer was grown via a 3C-SiC intermediate layer. A significantly low parasitic pad capacitance and a comparable cutoff frequency of 4.5 GHz for 2-μm gate length devices were achieved along with excellent electron transport characteristics, such as a mobility of ~2200 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V-s and a drain current density of 520 mA/mm. The extracted small-signal equivalentcircuit parameters also verified the accuracy of the measured cutoff frequency and parasitic capacitances.

Bias-Dependent Electron Velocity Extracted From N-Polar GaN Deep Recess HEMTs

This article reports on the extraction of the electron velocity as a function of gate bias from N-polar GaN deep recess high-electron-mobility transistors (HEMTs) designed for mm-wave power amplification. Bias-dependent small-signal S-parameter measurements are used to obtain small-signal equivalent circuit parameters, which are applied to a transit delay model. The model accounts for fringing capacitance to arrive at an electron velocity associated with the transit of the physical gate length. A peak electron velocity of $1.4\times 10^{{7}}$ cm/s was obtained at a drain current of 700 mA/mm corresponding to a channel charge density of $0.3\times 10^{{13}}$ cm−2. At higher current, the velocity slowly decreased with the electron velocity crossing below $10^{{7}}$ cm/s at 1.8 A/mm. This behavior was found to be in good agreement with a previously proposed model based on optical phonon scattering at the source injection point. An analysis of the delay components is used to provide guidance for the factors influencing the device performance.

Extraction of admittance parameters of symmetrically doped AlGaN/GaN/AlGaN DH-HEMT for microwave frequency applications

An analytical model for determining intrinsic short-circuit admittance (Y) parameters of AlGaN/GaN/AlGaN Double Heterostructure (DH) High Electron Mobility Transistor (HEMT) is presented. These Y parameters obtained in terms of the various small signal equivalent circuit parameters are in turn used to evaluate the enhanced microwave performance of the DH-HEMT in terms of various parameters including Unilateral Power Gain and maximum oscillation frequency. The cut-off frequency has been evaluated from short circuit current gain. The cut-off frequency (fT) and maximum oscillation frequency (fmax) exhibited for DH-HEMT is 125 GHz and 215 GHz which is comparatively improved as obtained in Single Heterostructure (SH) HEMT (fT = 105 GHz and fmax = 165 GHz). The analytical results obtained for DH and SH-HEMT; have been compared and found to match well with the ATLAS 2D device simulation results thus proving the validity of the model.

Effects of Self-Heating on ${f}_{\text{T}}$ and ${f}_{\text{max}}$ Performance of Graphene Field-Effect Transistors

It has been shown that there can be a significant temperature increase in graphene field-effect transistors (GFETs) operating under high drain bias, which is required for power gain. However, the possible effects of self-heating on the high-frequency performance of GFETs have been weakly addressed so far. In this article, we report on an experimental and theoretical study of the effects of self-heating on dc and high-frequency performance of GFETs by introducing a method that allows accurate evaluation of the effective channel temperature of GFETs with a submicrometer gate length. In the method, theoretical expressions for the transit frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and the maximum frequency of oscillation (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) based on the small-signal equivalent circuit parameters are used in combination with the models of the field- and temperature-dependent charge carrier concentration, velocity, and saturation velocity of GFETs. The thermal resistances found by our method are in good agreement with those obtained by the solution of the Laplace equation and by the method of thermo-sensitive electrical parameters. Our experiments and modeling indicate that the self-heating can significantly degrade the f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of GFETs at power densities above 1 mW/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , from approximately 25 to 20 GHz. This article provides valuable insights for further development of GFETs, taking into account the self-heating effects on the high-frequency performance.

Uniformity investigation of pHEMTs small-signal parameters for pre and post multilayer fabrication in 3D MMICs

The main aim of this paper is to investigate the uniformity of pHEMTs small-signal parameters before and after multilayer fabrication in 3D MMICs. Seven samples of pre-and post-multilayer fabricated pHEMTs at different representative locations to reflect the degree of consistency. This study deals with the fabrication, measurement, simulation, and comparison of both sample in form of means and slandered deviation. On wafer scattering (S-) parameter measurement has been accomplished to investigate the small signal equivalent circuit parameters up to 50 GHz. The main finding was observed that all parameters are increased after multilayer fabrication except the transconductance and the parasitic inductances. The employment of the 3D-MMIC technology does not induce any evident extinction of the pHEMTs performance utilizing seven different samples of pre-and post-multilayer fabrication.

Microwave frequency small-signal equivalent circuit parameter extraction for AlInN/GaN MOSHEMT

This article presents an accurate and efficient extraction procedure for microwave frequency small-signal equivalent circuit parameters of AlInN/GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMT). The parameter extraction technique is based on the combination of conventional and optimization methods using the computer-aided modeling approach. The S-, Y-, and Z- parameters of the model are extracted from extensive dynamic AC simulation of the proposed device. From the extracted Y- and Z- parameters the pad capacitances, parasitic inductances and resistances are extracted by operating the device at low and high frequency pinch-off condition depending upon requirement. Then, the intrinsic elements are extracted quasi analytically by de-embedding the extrinsic parameters. S-parameter simulation of the developed small-signal equivalent circuit model is carried out and is compared with TCAD device simulation results to validate the model. The gradient based optimization approach is used to optimize the small-signal parameters to minimize the error between developed SSEC model and device simulation based s-parameters. The microwave characteristics of optimized SSEC model is carried out (fT = 169 GHz and fmax = 182 GHz) and compared with experimental data available from literature to validate the model.

GaN high electron mobility transistors for sub-millimeter wave applications

This paper reviews different technologies recently developed to push the performance of GaN-based high electron mobility transistors (HEMTs) into sub-mm wave frequencies. To understand the impact and need of each technology, a device delay model based on small-signal equivalent circuit parameters is introduced, which divides the total device delay into intrinsic, extrinsic, and parasitic components. Then, several technologies to improve the speed of GaN HEMTs are discussed according to their contribution on each delay component. Finally, the key limiting factors for the high speed operation of these transistors under high drain or gate bias range are studied and novel approaches to solve these problems are presented.

Small- and large-signal modeling of InP HBTs in transferred-substrate technology

In this paper, the small- and large-signal modeling of InP heterojunction bipolar transistors (HBTs) in transferred substrate (TS) technology is investigated. The small-signal equivalent circuit parameters for TS-HBTs in two-terminal and three-terminal configurations are determined by employing a direct parameter extraction methodology dedicated to III–V based HBTs. It is shown that the modeling of measured S-parameters can be improved in the millimeter-wave frequency range by augmenting the small-signal model with a description of AC current crowding. The extracted elements of the small-signal model structure are employed as a starting point for the extraction of a large-signal model. The developed large-signal model for the TS-HBTs accurately predicts the DC over temperature and small-signal performance over bias as well as the large-signal performance at millimeter-wave frequencies.

Impact of Temperature and Indium Composition in the Channel on the Microwave Performance of Single-Gate and Double-Gate InAlAs/InGaAs HEMT

This paper presents an accurate charge control-based analytical model for investigating the impact of temperature variation in a broad range from -50 °C to 200 °C and the impact of indium composition variation in the channel on the small-signal equivalent circuit parameters of single-gate (SG) and double-gate (DG) In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.48</sub> As/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-m</sub> As (0.53 ≤ m ≤ 0.8) high electron mobility transistor (HEMT). The drain current and the various small-signal equivalent circuit parameters including the transconductance and the gate capacitances which are considered as the major factors governing the microwave performance of the device are observed to be more sensitive to temperature variation in the case of DG-HEMT as compared to the SG-HEMT. The increase in the indium composition in the In m Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-m</sub> As channel from to results in improved cutoff frequency of the device. However, the degradation in the cutoff frequency with increase in temperature increases with increase in the indium content in the channel. The results obtained from the proposed analytical model are compared and found to be in good agreement with the ATLAS device simulation results.

Comprehensive Study on the Bias-Dependent Equivalent-Circuit Elements Affected by PECVD SiN Passivation in AlGaN/GaN HEMTs

In this paper, a comprehensive study on the effect of plasma-enhanced chemical-vapor-deposited SiN surface passivation on the bias-dependent small-signal equivalent-circuit elements is carried out for AlGaN/GaN high-electron mobility transistors on a high-resistivity silicon substrate. The direct-current and small-signal performance of the device was found to be improved by surface passivation. The small-signal equivalent-circuit parameters at various gate and drain biases were extracted, and the physical mechanisms of their bias-dependent behaviors before and after passivation are discussed in detail.

Analytical Modeling of High-Frequency Noise Including Temperature Effects in GaN HEMTs on High-Resistivity Si Substrates

In this paper, analytical modeling of high-frequency noise was carried out including temperature effects in AlGaN/GaN high electron mobility transistors (HEMTs) on high-resistivity Si substrates over a wide temperature range from -50°C to 200°C. The device's microwave S-parameters and overall noise parameters, including minimum noise figure (NFmin), equivalent noise resistance (Rn) , and optimum source reflection coefficient (|⌈opt| and ∠⌈opt) were measured over the whole temperature range. Its small signal equivalent circuit parameters (ECPs) and internal noise source coefficients (P, R, and C) were extracted at each measurement temperature and their temperature variances were fitted using a quadratic relationship. An analytical model of the overall noise parameters is proposed based on Pucel's PRC theory. It is compared with two other commonly used analytical models and verified with the measured data, including temperature dependence. The feedback capacitance Cgd was found to be important to accurately simulate all the measured noise parameters over temperature.

An analytic procedure for extraction of metallic collector-up InP/InGaAsP/InGaAs HBT small signal equivalent circuit parameters

A parameter extraction procedure for determining an improved T-topology small signal equivalent circuit of a metallic collector-up HBT with composite base is presented. The proposed T-small signal equivalent circuit includes base and collector impedances modelled by parallel RC circuits. The new technique employs analytically derived expressions for direct calculation of HBT T-Model equivalent circuit element values in terms of the measured S-parameters. This approach avoids errors due to uncertainty in fitting to large, over determined equivalent circuits and does not require the use of test structures and extra measurement steps to evaluate parasitics. Physically realistic results are demonstrated under various biasing conditions for the n–p–n InP/InGaAsP/InGaAs composed base HBT with metallic collector-up structure (C-up MHBT). The agreement between the measured and model-produced data is excellent over the large frequency range and for several polarizations conditions for devices.

An Improved Small-Signal Parameter-Extraction Algorithm for GaN HEMT Devices

A highly efficient and accurate extraction algorithm for the small-signal equivalent-circuit parameters of a GaN high electron-mobility device is presented. Elements of the extrinsic equivalent-circuit topology are evaluated using a modified cold field-effect transistor approach whereby the undesirable need to forward bias the device's gate terminal is avoided. Intrinsic elements are determined based on a circuit topology, which identifies, for the first time, a time delay in the output conductance of GaN-based devices. The validity of the proposed algorithm has been thoroughly verified with excellent correlation between the measured and modeled S-parameters up to 50 GHz.

Direct Analysis Technique for Long-Finger HBT by Electromagnetic and Device Co-Simulation

This paper presents a direct-analysis technique for transistors with a long-finger structure. The analysis technique is an incorporated simulation between the finite-difference time-domain electromagnetic (EM) and semiconductor device simulations. The co-simulation method can consider various EM couplings and phase shifts on finger electrodes of transistors. The method was applied for InGaP/GaAs HBTs with various finger lengths to investigate gain degradation characteristics as a function of the finger length. As the first step, circuit simulations were done instead of a semiconductor device simulation using SPICE models of the HBT. Both large- and small-signal equivalent-circuit parameters were extracted by measurements to estimate nonlinear and linear characteristics, respectively. Using the extracted small-signal parameters, the gain degradation was estimated. The co-simulation results showed the same tendency as measurement results. Additionally, it was numerically shown that a resistive loss was mainly affected for the gain degradation from a comparison between gold and lossless electrodes.

A 7-dB 43-GHz CMOS Distributed Amplifier on High-Resistivity SOI Substrates

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents designs and measurements of distributed amplifiers (DAs) processed on a 130-nm silicon-on-insulator CMOS technology on either standard-resistivity (<formula formulatype="inline"><tex>${{\hbox{10}} \ \Omega \cdot {\hbox {cm}}}$</tex></formula>) or high-resistivity <formula formulatype="inline"><tex>$({&gt;}{\hbox{1 k}}\Omega \cdot {\hbox {cm}}$</tex> </formula>) substrates, and with either body-contacted (BC) or floating-body (FB) MOSFETs. Investigations have been carried out to assess the impact of active device performance and transmission line losses on circuit design by means of simulations, analytical calculations, and comparisons of the small-signal equivalent-circuit parameters. On standard-resistivity substrates, DAs with FB devices and lossy microstrip lines on thin film exhibit a measured gain of 7.1 dB and a unity-gain bandwidth (UGB) of 27 GHz for a dc power consumption of 57 mW. With the introduction of high-resistivity substrates, other DAs, with the same architecture and using lower loss coplanar waveguide lines, show a UGB of 51 GHz with FB devices and 47 GHz with BC devices. To the authors' knowledge, the designs presented in this paper achieve the best tradeoffs in terms of gain, bandwidth, and power consumption for CMOS-based circuits with comparable architecture. </para>

Fabrication and characterization of 4H-SiC planar MESFETs

The planar 4H-SiC MESFETs were fabricated by employing an ion-implantation process instead of a recess gate etching process, which is commonly adapted in compound semiconductor MESFETs, to eliminate potential damage to the gate region during etching process. Excellent ohmic and Schottky contact properties were achieved by using the modified RCA cleaning of 4H-SiC surface and the sacrificial thermal oxide layer. The fabricated MESFETs was also free from drain current instability, which the most of SiC MESFETs have been reported to suffer for the charge trapping. The drain current recovery characteristics were also improved by passivating the surface with a thermal oxide layer and eliminating the charge trapping at the surface. The performance of fabricated MESFETs was characterized by analyzing the small-signal equivalent circuit parameters extracted from the measured parameters.

Analysis of DC Characteristics and Small Signal Equivalent Circuit Parameters of GaAs Metal–Semiconductor Field Effect Transistors with Different Gate Lengths and Different Gate Contours by Two-Dimensional Device Simulations

The gate length and gate contour of a GaAs metal–semiconductor field effect transistor (MESFET) device play important roles in determining the small signal circuit parameters and large signal breakdown voltage behavior. GaAs MESFETs with different gate lengths and gate contours were studied by the two-dimensional (2-D) semiconductor device simulations to investigate the dependence of small signal circuit parameters and breakdown voltage on gate length and gate contour. The results show that gate length affects small-signal circuit parameter Cgs while gate contour affects Cgd. The breakdown voltage has strong dependence on gate contour and little dependence on gate length.

A Pure Analytic Method for Direct Extraction of Collector-Up HBT's Small-Signal Parameters

A pure analytic procedure for direct extraction of the small-signal equivalent-circuit parameters, including extrinsic inductances, has been demonstrated and successfully applied to III-V and SiGe collector-up heterojunction bipolar transistors (HBTs). This method can alleviate some difficulties encountered among conventional extracting techniques that are the use of additional test structures, forward-biased measurements at specific bias conditions, and empirical optimization process. In this paper, the hybrid-/spl pi/ equivalent-circuit elements are extracted in a simple and efficient way from impedance and admittance formulation on the basis of measured S-parameters. To study the bias dependence, the extrinsic and intrinsic circuit components are evaluated under different bias conditions. The model parameters are sequentially derived during the extraction process yielding a full set of physical element values. The validity of our model is explored on pnp collector-up AlGaAs-InGaAs HBTs, and a good coincidence between measured and modeled S-parameters is observed for the entire frequency range of operation. Consistent extracted trends indicate that this improved equivalent-circuit model is suitable to be implemented in circuit simulators for microwave-circuit TCAD applications.

Simulation studies of a 2 Gb s−1 monolithic integrated smart pixel based on fabricated p-i-n PD, DHBT and a VCSEL

A smart pixel that can function as a building block of an optical transceiver with circular dimensions is proposed using InGaP/GaAs double heterojunction bipolar transistors (DHBTs) and a GaAs/AlGaAs vertical cavity surface emitting laser (VCSEL). Fabricated DHBT showed a breakdown voltage of 13 V and a cut-off frequency of 35 GHz at Ic = 30 mA. Also a high-performance 850 nm infra-red VCSEL exhibited a threshold current of 3.5 mA with a maximum optical output of 4.8 mW at Ic = 20 mA and forward voltage of 1.8 V. The detector, comprised of the base-to-collector junction of the DHBT as a pin-PD, produced a photocurrent of 180 µA for a given input power of 0.3 mW. The extracted small-signal equivalent circuit parameters from measurement of these devices were used in PSPICE simulations to design an interface drive circuit for high-speed modulation. The overall OEIC circuit performance operates up to data rates of 2 Gb s−1 at 1 mW output power with maximum output voltage of 2 V across the VCSEL and modulation current of 5 mA.