Slower Threads Research Articles

Reinforcement learning-based register renaming policy for simultaneous multithreading CPUs

Simultaneous multithreading (SMT) improves the performance of superscalar CPUs by exploiting thread-level parallelism with shared entries for better utilization of resources. A key issue for this out-of-order execution is that the occupancy latency of a physical rename register can be undesirably long due to many program execution-dependent factors that result in performance degradation. Such an issue becomes even more problematic in an SMT environment in which these registers are shared among concurrently running threads. Smartly managing this critical shared resource to ensure that slower threads do not block faster threads’ execution is essential to the advancement of SMT performance. In this paper, an actor–critic style reinforcement learning (RL) algorithm is proposed to dynamically assigning an upper-bound (cap) of the rename registers any thread is allowed to use according to the threads’ real-time demand. In particular, a critic network projects the current Issue Queues (IQ) usage, register file usage, and the cap value to a reward; an actor network is trained to project the current IQ usage and register file usage to the optimal real-time cap value via ascending the instructions per cycle (IPC) gradient within the trajectory distribution. The proposed method differs from the state-of-the-art (Wang and Lin, 2018) as the cap for the rename registers for each thread is adjusted in real-time according to the policy and state transition from self-play. The proposed method shows an improvement in IPC up to 162.8% in a 4-threaded system, 154.8% in a 6-threaded system and up to 101.7% in an 8-threaded system. The code is now available open source at https://github.com/98k-bot/RL-based-SMT-Register-Renaming-Policy.

System performance enhancement with thread suspension for simultaneous multi-threading processors

ABSTRACT Simultaneous Multi-Threading systems improve performance by allowing multiple independent threads to be executed concurrently with shared key resources. Unfair sharing of resources among multiple threads can easily clog the pipeline stages by slower threads and hamper the normal processing of faster threads. In this paper, we propose a thread-suspension scheme combined with a uniform register file capping technique to avoid imbalanced distribution of resources. When a shared resource congestion occurs on the pipeline stages, the thread with the lowest resource utilization efficiency among all active threads will be suspended so as to provide other threads more space to proceed for a higher throughput. Our experimental results show that our proposed technique improves the average system throughput in terms of Instruction Per Clock Cycle by up to 51.3%, with little compromise in execution fairness.

An integrated autonomous control mechanism to optimize sharing of multiple resources in Simultaneous Multi-Threading processors

Abstract Simultaneous Multi-Threading (SMT) processors allow concurrent execution of multiple independent threads with sharing of key datapath components to enhance system performance with more efficient resource utilization. However, due to the nature of SMT processing, imbalanced distribution of critical shared resources may easily clog some pipeline stages by slower threads and lead to unexpected system performance degradation. In this paper, an integrated autonomous control mechanism is proposed to optimize the use of two critical shared resources among multiple threads based on threads’ temporal behaviors in real time, by taking into account resource utilization snapshots at various stages of the pipeline. Our simulations based on M-Sim (Sharkey, 2005) [1] show that our proposed mechanism improves IPC (Instruction Per Clock Cycle) by a very significant margin (up to 100.4%) without sacrificing execution fairness among threads. Performance improvement from the proposed integrated approach on the two shared resources easily surpasses the aggregated benefits from two control mechanisms with each considering only one individual resource at a time.

A controlled fetching technique for effective management of shared resources in SMT processors

Simultaneous Multi-Threading (SMT) is a processor design technique that supports concurrent execution of instructions from multiple threads in every cycle by sharing the key datapath components. In the SMT architecture, the shared resources normally include the physical register file, Issue Queue (IQ), functional units, write buffer and the cache memory. Efficient utilization of the shared resources is critical to achieving high-performance gain. The physical rename register file is one of the most critical shared resources in the SMT architecture due to its being located at forefront of the pipeline stages. The inter-thread sharing of the physical registers reduces the number of registers required in the SMT processors than would have been needed in deploying multiple superscalar processors to achieve a similar throughput. However, due to the nature of sharing, an overwhelming occupancy of the physical register file by any slower threads can lead to a shortage of registers available for the other threads in the system and thus degrade the overall performance. In this paper, we propose an intelligent fetching algorithm for efficient management of the shared physical register file. Even though the primary focus of this paper is to manage the physical register file effectively, it indirectly controls the other shared resources downstream in the pipeline as well. The main goal of this paper is to propose a simple resource management scheme capable of achieving a considerable performance gain that neither incurs a substantial processing or hardware overhead for practical implementation nor requires modifications in the other pipeline stages. We demonstrate that temporarily suspending the slow threads from the system in the fetch stage can improve the overall system performance by a significant margin. An improvement of up to 63% and 68% is achieved when the proposed scheme is applied to the 4-threaded and the 8-threaded system respectively. The throughput of an 8-threaded system with 320 register file entries is significantly higher than the performance of default system with 416 register entries indicating a resource saving of 60%.

Efficient resource sharing algorithm for physical register file in simultaneous multi-threading processors

Simultaneous Multi-Threading (SMT) processors increase performance by allowing concurrent execution of multiple independent threads with sharing of key datapath components and better utilization of the resources. An SMT processor usually maintains a shared register file to accommodate multiple threads for register renaming. By supporting inter-thread sharing of the physical registers, an SMT system processor can reduce the number of registers that would have been required in multiple superscalar processors while achieving a comparable throughput. However, congested shared resources due to slower threads can easily lead to inefficient usage of the resources and thus an undesirable performance outcome. In this paper, we propose an allocation algorithm at the architectural level for a better utilization of the shared register file. We show that, by limiting the number of the physical register entries each thread is allowed to occupy at any given time, the overall system throughput is enhanced by a substantial margin. An improvement in IPC of up to 44.6% and 32.7% is observed when the proposed technique is applied to a 4-threaded and a 6-threaded SMT system, respectively. Furthermore, a 4-threaded system with a physical register file of 160 entries can deliver a performance comparable to that of a default system with 256 entries, reflecting a resource saving of 37.5%.

The Role of the Threading Moiety in DNA Threading Intercalation by Ruthenium Dimer Complexes

There is significant interest in ruthenium dimer complexes due to their novel DNA binding properties. The binuclear ruthenium complex ΔΔ-[μ-bidppz(bipy)4Ru2]4+ that we investigate in this study binds to DNA by threading intercalation, in which one of the bulky ruthenium moieties threads through the DNA base pair stack to reach its bound state. The extremely slow dissociation from DNA of this threading intercalator gives it properties needed for chemotherapy drugs, while also making it difficult to study in traditional bulk experiments. In this study we use optical tweezers in order to quantify the threading kinetics as well as the equilibrium behavior of this ruthenium dimer complex to understand how changing the ancillary ligands coordinated to ruthenium (threading moiety) affects the process of threading. To observe the slow threading process, the DNA was held at a constant force in the presence of the ligand and the DNA extension was measured as a function of time until the extension reached equilibrium. When the concentration of the ligand is increased during these constant force measurements, the total extension of the DNA will also increase until it becomes saturated at some concentration as all of the ligand binding sites are filled. These measurements of the equilibrium DNA extension allow for a full quantitative description of the binding kinetics and equilibrium behavior of the complex. The preliminary data suggests that the ΔΔ-[μ-bidppz(bipy)4Ru2]4+ complex with its bicyclic bipyridine ligand, shows significantly faster kinetics compared to the ΔΔ-[μ-bidppz(phen)4Ru2]4+, complex with a tricyclic phenanthroline ligand counterpart.

Orientational isomers of α-cyclodextrin [2]semi-rotaxanes with asymmetric dicationic threads

Two series of novel dicationic threading molecules [Quin(CH2)10R]2+ and [3,5-Lut(CH2)10R]2+, where Quin+ = quinuclidinium, 3,5-Lut+ = 3,5-lutidinium, and R+ = N(CH3)3+ and N(CH3)2CH2CH3+, form [2]semi-rotaxanes with [small alpha]-cyclodextrin (alpha-CD) in aqueous solution. The quinuclidinium and 3,5-lutidinium are sufficiently bulky to prevent threading while the R+ groups allow for slow threading by alpha-CD at 25 degrees C. The resulting [2]semi-rotaxanes exist in two orientational isomers owing to the asymmetry of both the alpha-CD cavity and the threading molecules. Two-dimensional 1H NMR spectroscopy and kinetics experiments reveal that the isomer in which the narrower rim (primary OHs) is positioned near the R+ group is the kinetically preferred isomer, while the other isomer is the thermodynamically preferred product. The kinetics and mechanism of the formation, dissociation, and interconversion of the two isomers have been determined at 25 degrees C.

The self-assembly of a [2]pseudorotaxane of α-cyclodextrin by the slippage mechanism

The kinetics and thermodynamics of the self-assembly of a [2]pseudorotaxane comprised of α-cyclodextrin and the 1,10-bis[1-(4-tert-butylpyridinium)]decane dication, by means of a slippage procedure, have been measured in aqueous solutions using 1H NMR spectroscopy. The very slow threading of the α-cyclodextrin [k1=(4.2 ± 0.3)× 10–4 s–1 at 25 °C] is preceded by a weak inclusion of the tert-butylpyridinium end group (KCD= 18 ± 3 dm3 mol–1). The dissociation of the [2]pseudorotaxane occurs with a rate constant of (4.2 ± 0.2)× 10–6 s–1 at 25 °C, yielding a pseudorotaxane stability constant of (1.8 ± 0.2)× 103 dm3 mol–1.

Application of Low Frequency to Industrial Control Problems

The performance of an induction motor on low-frequency voltages is readily predictable by means of the relations shown in Appendix I. We find from these relations that full torque is available from the motor providing the impressed frequency is at least equal to the slip frequency at which this torque would normally occur. The change in speed from full load to no load under the foregoing conditions is approximately the same as under normal operating conditions. Small high-speed machines can be effectively employed in generating the voltages needed for low-frequency operation. Although the generating system which we have described is best suited to supplying one frequency, a selection of frequencies and speeds can be obtained by simultaneously switching the relatively low current exciting circuits to provide the necessary change in circuit constants for different frequencies. Speed control in the manner described is particularly useful in applications requiring several induction motors to be started either individually or simultaneously without immediately accelerating to a high speed. This feature is required in printing press and other drives where a number of individual units are flexibly interconnected. The ease with which these units can be arranged in various combinations is greatly enhanced if they can be individually driven. Ordinary wound rotor induction motor control does not provide the required slow threading speeds and the use of individual gear shifting or other mechanical speed changers complicates the mechanical system. The use of a low-frequency power source is one solution to this type of problem.