Slow Trap Research Articles

Trap properties of high-k/metal gate pMOSFETs with aluminum ion implantation by random telegraph noise and 1/f noise measurements

In this study, the impact of aluminum ion implantation on 1/f noise characteristics and random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) was investigated. Aluminum ion implantation (Al I/I) into TiN/HfO2/SiO2 was implemented to tune an effective work function (EWF) in pMOSFETs without EOT increase complicated processes. RTN and 1/f results revealed that regardless of the implanted dose, HK/MG devices with Al I/I exhibit lower slow oxide trap densities than the control devices, which are responsible for the reduced trap position (xt) from the SiO2 interfacial layer (IL)/Si interface. For the HK/MG devices with different implanted doses, no significant differences in trap properties were observed.

Process Temperature Dependence of Al2O3Film Deposited by Thermal ALD as a Passivation Layer for c-Si Solar Cells

This paper presents a study of the process temperature dependence of Al₂O₃ film grown by thermal atomic layer deposition (ALD) as a passivation layer in the crystalline Si (c-Si) solar cells. The deposition rate of Al₂O₃ film maintained almost the same until 250 ℃, but decreased from 300 ℃. Al₂O₃ film deposited at 250 ℃ was found to have the highest negative fixed oxide charge density (Qf) due to its O-rich condition and low hydroxyl group (-OH) density. After post-metallization annealing (PMA), Al₂O₃ film deposited at 250 ℃ had the lowest slow and fast interface trap density. Actually, Al₂O₃ film deposited at 250 ℃ showed the best passivation effects, that is, the highest excess carrier lifetime (τPCD) and lowest surface recombination velocity (Seff) than other conditions. Therefore, Al₂O₃ film deposited at 250 ℃ exhibited excellent chemical and field-effect passivation properties for p-type c-Si solar cells.

Positive Bias Instability and Recovery in InGaAs Channel nMOSFETs

Instability of InGaAs channel nMOSFETs with the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> / ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interfacial layer (IL), the slow trapping at which is responsible for the power law time dependency of the threshold voltage shift and transconductance change. The fast electron trapping in the ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film exhibits negligible recovery, in contrast to the Si-based devices with a similar high-k dielectric film. Generation of new electron trapping defects is found to occur in the IL, preferentially in the region close to the substrate, while trap generation in the high-k dielectric is negligible.

Low-temperature fabrication of Y2O3/Ge gate stacks with ultrathin GeOx interlayer and low interface states density characterized by a reliable deep-level transient spectroscopy method

Y2O3/Ge gate stacks with ultrathin GeOx interlayer were fabricated by two-step rf sputtering using a Y2O3 target followed by a vacuum-annealing, which were carried out in the same chamber without vacuum breaking. TiN-gate Ge metal–insulator–semiconductor (MIS) capacitors were fabricated with equivalent oxide thicknesses in the range of 2.1–2.3nm. The highest temperature was 400°C for the entire fabrication process. Interface states density (Dit) was characterized using a deep-level transient spectroscopy method with optimized injection pulse and quiescent reverse-bias voltages at each temperature. Dit values were approximately 4×1013, 5×1011, and 3×1012cm−2eV−1 at energy positions around valence band, mid-gap, and conduction band, respectively. The slow trap contribution was also small in the upper half of the band-gap, implying a potential application of the Y2O3/Ge gate stack to the fabrication of high-performance Ge-n-MIS field effect transistors.

Operational stability enhancement of low-voltage organic field-effect transistors based on bilayer polymer dielectrics

Bilayer polymer dielectrics consisting of hydrophobic thin layers on high-k polyvinylalcohol (PVA) are utilized to realize p-type and n-type low-voltage organic field-effect transistors (OFETs), which show superior mobility and operational stability compared with the devices with PVA single-layer dielectric. The OFETs with top layers containing discrete π-groups, such as polystyrene (PS) and poly(2-vinyl naphthalene) (PVN), show stronger bias stress instability than those with π-group free polymethylmethacrylate (PMMA), and it is ascribed to slow charge trapping into the π-groups under bias stress. By integrating p-type and n-type low-voltage OFETs based on PMMA/PVA bilayer dielectric, a low-power high-stability complementary inverter is achieved.

Solution-Processed Dual-Gate Polymer Field-Effect Transistors for Display Applications

We describe the advantages of dual-gate thin-film transistors (TFTs) for display applications. We show that in TFTs with active semiconductor layers composed of diketopyrrolopyrrole-naphthalene copolymer, the on-current is increased, the off-current is reduced, and the sub-threshold swing is improved compared to single-gate devices. Charge transport measurements in steady-state and under non-quasi-static conditions reveal the reasons for this improved performance. We show that in dual-gate devices, a much smaller fraction of charge carriers move in slow trap states. We also compare the activation energies for charge transport in the top-gate and bottom-gate configurations.

Trapping phenomena in AlGaN/GaN HEMTs: a study based on pulsed and transient measurements

Slow trapping phenomenon in AlGaN/GaN HEMTs has been extensively analyzed and described in this paper. Thanks to a detailed investigation, based on a combined pulsed and transient investigation of the current/voltage characteristics (carried out over on an 8-decade time scale), we report a detailed description of the properties of trap levels located in the gate–drain surface, and in the region under the gate of AlGaN/GaN HEMTs. More specifically, the following, relevant results have been identified: (i) the presence of surface trap states may determine a significant current collapse, and reduction of the peak transconductance. During a current transient measurement, the emission of electrons trapped at surface states proceeds through hopping, as demonstrated by means of temperature-dependent measurements. The activation energy of the de-trapping process is equal to 99 meV. (ii) The presence of a high density of defects under the gate may induce a significant shift in the threshold voltage, when devices are submitted to pulsed transconductance measurements. The traps responsible for this process have an activation energy of 0.63 eV, and are detected only on samples with high gate leakage, since gate current allows for a more effective charging/de-charging of the defects.

Effects of post-deposition annealing ambient on chemical, structural, and electrical properties of RF magnetron sputtered Y2O3 gate on gallium nitride

The influence of post-deposition annealing (PDA) ambient [O2, Ar, forming gas (FG; 95% N2–5% H2), and N2] on chemical, structural, and electrical properties of RF magnetron sputtered Y2O3 films on gallium nitride (GaN) had been investigated. X-ray photoelectron spectroscopy revealed that the bulk oxide annealed in different ambient was composed of Y–O and Y–N bonds while the interfacial layer (IL) was comprised of a mixture of Ga–O, Y–O, Ga–O–N, and Y–N bonding. It was also detected that oxygen trapping happened in the bulk oxide for all of the investigated samples but this oxygen trapping ensued until the region of IL for sample annealed in O2 ambient. The Y2O3 film subjected to PDA in N2 ambient was in amorphous structure as no Y2O3 phase was able to detect by X-ray diffraction (XRD). When PDA was performed in O2, Ar, and FG ambient, polycrystalline phase of Y2O3 was detected. Besides, XRD results also revealed β-Ga2O3 phase for all samples. A correlation between the chemical and structural results with metal–oxide–semiconductor (MOS) characteristics of Y2O3/GaN structure subjected to different PDA ambient has been established. Of these investigated samples, sample annealed in O2 ambient possessed the lowest leakage current and the highest electric field (∼6.6 MV/cm) at 10−6 A/cm2 due to the attainment of the lowest interface trap density, total interface trap density, and slow trap density as well as the presence of positive effective oxide charge.

First demonstration of device-quality symmetric N-MOS and P-MOS capacitors on p-type and n-type crystalline Ge substrates

Ge interface nitride passivation.Si passivation layer thickness.SiON surface on Si passivation layer.Anneal to eliminate Ge-N bonds.Symmetric NMOS and CMOS capacitors. Three significant issues with respect to the ultimate scaling limitations of CMOS devices are (i) the channel or transport material, (ii) high-? compatible gate stacks: (a) the interface with the semiconductor substrate; (b) the high dielectrics, and (c) the gate metal, and (iii) the topological structure, planar, nano-tube, or in, etc. Two of these are high-lighted, focusing on (i) crystalline Ge, and transition metal dielectrics including specifically non-crystalline Hf Si oxynitrides, and nano-grain (a) ultra-thin 2nm thick HfO2 and TiO2. The research has demonstrated shallow trap interfacial slow trap densities of ~5i?1010cm-2, no detectable negative bulk fixed charges, and symmetric N- and P-MOCAPS in planar geometries. EOT values <0.5nm were obtained for low-leakage current for N-MOSCAPS with ng-TiO2 in contact with plasma processed c-Ge substrates.

Gain-assisted trapping of light in tapered plasmonic waveguide

We have investigated the slow light and trapping effects in tapered metal-insulator-metal plasmonic waveguides. It is found that a significant reduction of group velocity (<0.01c) can be obtained when considering the intrinsic loss of realistic metal. The theoretical analysis shows that the group velocity can be further decreased, even approach zero in the lossless metallic waveguides. The perfect trapping of light is realized when an appropriate gain material is incorporated in the core layer to compensate metallic loss. The proposed ultracompact configuration may find excellent applications on nanoscale optical storages.

Investigation of defect generation and annihilation in IGZO TFTs during practical stress conditions: illumination and electrical bias

This investigation elucidates the influence of standalone-bias stress and standalone-illumination stress, and their combinatory effect on indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). Each phenomenon associated with illumination (wavelengths of 410, 467, 532 and 632 nm) and bias (Vg = ±20 V; Vd = 0, 20 V) stresses is categorized individually. Wavelengths below 532 nm are responsible for ionized vacancy creation, carrier generation and interface state creation while only gate stresses of +20 V create excessive charge trap states. Failure conditions are identified as gate stresses of −20 V with 410 nm illumination. An improvement in the Ion/Ioff ratio from 106 to 107 is due to increased charge contribution for on currents, and trapping of holes at the intermetallic dielectric near the source–channel junction in the off region. Upon stress removal TFTs exhibit incomplete recovery due to slow trapping of excited carriers from dielectric layers and inability created by the passivation layer to absorb oxygen for vacancy regeneration. The low-temperature fabrication and optimized post-fabrication anneal have created reduced defect and vacancy densities that make the IGZO TFTs more stable than the previous generation TFTs.

Linking On-State Memory and Distributed Kinetics in Single Nanocrystal Blinking

Memory effects in single nanocrystal fluorescence blinking are investigated as a function of the on-state kinetics for CdSe/ZnS quantum dots and CdSe nanorods. The on-state duration probability distributions for single nanocrystal blinking traces are characterized by an inverse power law, which crosses over to exponential decay for long on-state durations. The correlations of subsequent on-state durations (Rlog,on) are found to decrease for nanocrystals that display earlier crossover times and smaller power law coefficients. Specifically, Rlog,on increases from 0.14 ± 0.02 to a saturation value of 0.44 ± 0.01 for nanocrystals with average crossover times of ~100 ms to more than 5.0 s, respectively. The results represent the first link between memory effects and blinking kinetics and are interpreted in the framework of two competing charge trapping mechanisms. A slow fluctuation-based trapping mechanism leads to power-law-distributed on durations and significant memory effects; however, the additional contribution of an ionization-induced trapping pathway is found to induce crossover to exponential decay and decreased memory. Monte Carlo simulations of nanocrystal blinking based on the two trapping mechanisms reproduce the experimental results, suggesting that the power law component and the memory effects correlate with a fluctuation-based mechanism. This effect is found to be universal, occurring for two nanocrystal morphologies and in blinking data measured using a wide range of continuous and pulsed excitation conditions.

The role of shallow traps in dynamic characterization of organic semiconductor devices

We present an analysis of charge mobility determination methods for the steady as well as the transient state and investigate shallow charge traps with respect to their dynamic behavior. We distinguish between fast and slow trap states in our numerical model corresponding to two characteristic regimes. The two regimes manifest themselves in both impedance spectroscopy and dark injection transient currents (DITC). Further we investigate the charge mobility obtained from dynamic simulations and relate it to the extracted charge mobility from steady-state current-voltage curves. To demonstrate the practical impact of these regimes, we apply our numerical model to the DITC that have commonly been used to determine the charge mobility in organic semiconductor devices. The obtained results from DITC studies strongly depend on the measurement conditions. Therefore we analyze the measurements of reference [Esward et al., J. Appl. Phys. 109, 093707 (2011)] and reproduce the effects of varying pulse off-times on the transient current qualitatively. Thus, our simulations are able to explain the experimental observations with the help of relaxation effects due to shallow traps.

IV, noise and electroluminescence analysis of stress-induced percolation paths in AlGaN/GaN high electron mobility transistors

Properties of stress-induced percolation paths in AlGaN in step-stressed AlGaN/GaN high electron mobility transistors are investigated in details. DC and transient gate and drain current analysis are combined with low frequency noise and electroluminescence measurements. The observation of random telegraph signal (RTS) noise with large relative amplitude indicates that RTS is due to modulation of gate current in the percolation path by action of single defects. Measurements of RTS amplitude as a function of forward or reverse gate voltage can reveal masked gate leakage current components related to individual percolation paths. The observed gradual increase in forward gate current ideality factor with progressing stress, indicating defect penetration inside the percolation path in AlGaN, is explained by a simple model. The role of slow trapping in the modulation of current in the percolation path is discussed too.

Preparation of Diamine‐β‐diketiminato Copper(II) Complexes and Their Application in the Reverse Atom‐Transfer Radical Polymerization of Styrene

AbstractCompound Et2NCH2CH2N=C(Me)CH=C(Me)NHCH2CH2NEt2 (HL), after conversion to the Li+ salt with use of MeLi, reacts with CuCl2 in toluene to yield CuClL (1). The compound adopts a four‐coordinate CuClN3 environment with a pendant amino arm. The same reaction with CuCl and[Cu(MeCN)4]BF4 leads to disproportionation with deposition of metallic copper. Crystals of compounds [CuL][CuCl2] (2) and [CuL]BF4 (3) were isolated in minor amounts from these reactions. The [CuL]+ ion in these compounds has a four‐coordinate CuN4 environment. Compound 2 was also obtained in good yields from the reaction between equivalent amounts of 1 and CuCl. Compound 1 was used to control the radical polymerization of styrene under ARGET ATRP conditions in the presence of glucose as reducing agent and bromoethylbenzene as initiator. The polymerization behavior indicates that the controlling ability of this system is negatively affected by its slow trapping rate and by the disproportionation of the CuL catalyst.

The Influence of Gate Material, SiO&lt;sub&gt;2&lt;/sub&gt; Fabrication Method and Gate Edge Effect on Interface Trap Density in 3C-SiC MOS Capacitors

This paper reports on results of interface trap analysis of 3C-SiC MOS capacitors fabricated using four different gate materials and two SiO2 oxide preparation methods. The results indicate that post-deposition annealing in wet oxygen of PECVD deposited SiO2 samples increases the near-interface or slow trap densities, compared with wet oxygen thermally oxidized samples. It has also been found that the energy distribution, Dit, of electron states at the oxide/SiC interface of MOS capacitors with different sizes depend on the factor R=P/A, where P stands for the gate perimeter and A for the gate area, which is related to the amount of stress under the edge of the metallic gate.

Oxide and interface trap densities estimation in ultrathin W/La2O3/Si MOS capacitors

A novel interpretation for conductance spectra obtained by conductance method of La2O3 gated MOS capacitors has been proposed. Two distinct peaks, one with broad spectrum ranging from 10k to 200kHz and the other near 1kHz with a single time constant spectrum, have been observed at depletion condition. The former spectrum can be assigned as the interface traps (Dit) located at the interface between La-silicate and the Si substrate by statistical surface potential fluctuation model. On the other hand, as the latter slow trap signal shows strong influence with the thickness of La-silicate layer, it can be assigned as the trappings (Dslow) at the interface between La2O3 and La-silicate. Finally, the Dit and Dslow trends on annealing temperature are summarized.

Effects of Post-Deposition Annealing Temperature on Band Alignment and Electrical Characteristics of Lanthanum Cerium Oxide on 4H-SiC

ABSTRACTInvestigation of lanthanum cerium oxide as a gate oxide on 4H-SiC was performed by varying post-deposition annealing temperature from 400 to 1000°C. Energy band alignment and band gap of bulk oxide and interfacial layer (IL) with respect to SiC were extracted using X-ray photoelectron microscopy. Two band alignment structures were proposed and the change of band alignment was affected by the changes in chemical composition in bulk oxide and in IL that may induce lattice strains and dipoles. A conduction band offset of IL/SiC was 0.97 eV for sample annealed at 1000°C, which was comparable to the value extracted from Fowler-Nordheim model. The acquisition of sufficient conduction band offset, coupled with the lowest slow trap density, effective oxide charges, interface trap density, as well as total interface trap density, yielded the lowest leakage current density for this sample.

Study of slow oxide trap creating random telegraph noise within a gate edge overlap region in inversion mode

We investigated a slow oxide trap causing a random telegraph noise (RTN) within a gate edge overlap region in an inversion mode at metal/high-k dielectric nMOSFETs. The oxide trap was observed to generate RTN only in gate leakage current (Ig RTN) without in drain current (Id RTN) in the inversion mode. Through the analysis of the RTN dependence on drain, source, and body bias, we found that the oxide trap in the dielectric exists not within the channel area but within the gate edge overlap region, resulting in the absence of Id RTN.

A special pair of phytohormones controls excitability, slow closure, and external stomach formation in the Venus flytrap

Venus flytrap's leaves can catch an insect in a fraction of a second. Since the time of Charles Darwin, scientists have struggled to understand the sensory biology and biomechanics of this plant, Dionaea muscipula. Here we show that insect-capture of Dionaea traps is modulated by the phytohormone abscisic acid (ABA) and jasmonates. Water-stressed Dionaea, as well as those exposed to the drought-stress hormone ABA, are less sensitive to mechanical stimulation. In contrast, application of 12-oxo-phytodienoic acid (OPDA), a precursor of the phytohormone jasmonic acid (JA), the methyl ester of JA (Me-JA), and coronatine (COR), the molecular mimic of the isoleucine conjugate of JA (JA-Ile), triggers secretion of digestive enzymes without any preceding mechanical stimulus. Such secretion is accompanied by slow trap closure. Under physiological conditions, insect-capture is associated with Ca(2+) signaling and a rise in OPDA, Apparently, jasmonates bypass hapto-electric processes associated with trap closure. However, ABA does not affect OPDA-dependent gland activity. Therefore, signals for trap movement and secretion seem to involve separate pathways. Jasmonates are systemically active because application to a single trap induces secretion and slow closure not only in the given trap but also in all others. Furthermore, formerly touch-insensitive trap sectors are converted into mechanosensitive ones. These findings demonstrate that prey-catching Dionaea combines plant-specific signaling pathways, involving OPDA and ABA with a rapidly acting trigger, which uses ion channels, action potentials, and Ca(2+) signals.