Slope Compensation Research Articles

Wideband 4×4 Nolen Matrix with 360° Continuously Tuned Differential Phase and Low In-Band Phase Deviation Error

In the paper, a wideband tunable 4×4 Nolen matrix is proposed. By using the presented topology of the Nolen matrix, tunable output port phase differences can be realized by inserting one type of tunable phase shifters (T-PS). Besides, the in-band phase deviation error is minimized by adding compensation phase shifters (C-PSs) to the output ports of the Nolen matrix. Analytical design methods based on signal flow graphs and complex exponential signal are given to obtain the rigorous relationships of the coupling and phase shifts in the Nolen matrix. Besides, a detailed method for output ports phase slope compensation is provided. For validation, a prototype centered at 5.8 GHz is designed and fabricated. Measurement results agree well with the simulated ones. By using only one voltage to control the phase shifts of the T-PS in a 90° range for each input excitation of the Nolen matrix, a full 360° range of the progressive phase difference is realized by switching four input ports. The measured fractional bandwidth under 10 dB return loss and isolation is larger than 24.5% with the in−band±1.5 dB amplitude imbalance and ±15° phase deviation error for ports 1-4 excitations. Besides, for a more strict criterion of ±1 dB amplitude imbalance and 10° phase deviation error, the measured bandwidths are larger than 15% for all port excitations.

Study and Modeling of Nonlinear Dynamic Characteristics of DC-DC Converters with Amnesia Loads

Abstract The chaos phenomenon is a seemingly random irregular motion occurring in a deterministic system, which is an inherent characteristic and prevalent phenomenon of amnesia-loaded DC-DC converter nonlinear systems. Nonlinear dynamics and chaos theory guide the text, and we create an amnesia-loaded DC-DC converter system model using an amnesia resistor. We analyze the stability of the system using Filippov theory, and analyze the nonlinear dynamic characteristic behavior of the amnesia-loaded DC-DC converter using the time-domain waveform diagram, bifurcation diagram, and phase-track diagram. This paper talks about the slope compensation method and the parametric resonance perturbation method for control analysis. These methods are used to stop the chaotic behavior that happens in the amnesia-loaded DCDC converter. The system maintains a stable state when the reference current is less than 4.732A and the supply voltage exceeds about 17.966V, maintaining an amplitude of the maximum eigenvalue below 1. When the load resistance is 50Ω, the capacitance is 43 uF, the inductance is 2.8 mH, and the reference voltage is 2.05 volts, the amnesia-loaded DC-DC converter suffers from obvious chaos. To restore the system to a steady state by applying the ramp compensation method, the slope of the ramp signal will need to increase as the reference current increases. Loading amnesia onto the DC-DC converter achieves a stable cycle 1 state when the perturbation phase’s fluctuation range falls between 4.35 and 6.15. A nonlinear dynamic analysis of the amnesia-loaded DC-DC converter helps find the stable parameters of the amnesia-loaded DC-DC converter and improve the design of the converter.

Integrated-optic chromatic dispersion compensator with completely passive operation and wide operational bandwidth

I report on a fiber chromatic dispersion compensator comprising an array of 100 fixed delay lines sandwiched by a pair of arrayed-waveguide grating-type wavelength filters. The requisite delay for the dispersion compensation is allocated to each demultiplexed wavelength component after the first wavelength filter, and the wavelength components are again multiplexed at the second filter. The flexible capability of delay pattern arrangement enables us to realize various fixed dispersion compensation characteristics. I show transmittance and relative delay time characteristics of a multichannel dispersion compensator for short-distance wavelength division multiplexing communication, and its application to dispersion compensation for a pulse amplitude modulation four signal. I also demonstrate the realization of a dispersion slope compensator for a dispersion-shifted fiber with this configuration.

MOSFET only low power sub‐bandgap voltage reference by subtraction of slope compensated proportional‐to‐absolute‐temperature voltage references

SummaryVoltage references are typically designed by combining a complimentary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltage references. However, in contrast to conventional voltage references, the proposed circuit generates a voltage reference by subtracting two PTAT voltages, resulting in an extremely low process‐dependent voltage reference. A novel subtractor is also proposed for subtracting PTAT voltages, which is used to generate the reference voltage. The temperature coefficient of the proposed voltage reference is further improved using a novel PTAT slope compensation technique. The proposed voltage reference is a MOS‐only ultra‐low power circuit that works with sub‐bandgap supply voltage. Simulation results using UMC 0.18 m technology MOSFETs show that the proposed circuit has a line sensitivity of 0.5%/V, a temperature coefficient of 21.37 ppm/° C, a power consumption of 15.6 nW, and an output voltage variation of only 0.22% due to process variations.

Adaptive slope compensation technology for current-mode controlled SIDO DC-DC converter in continuous conduction mode

Adaptive slope compensation technology for current-mode controlled SIDO DC-DC converter in continuous conduction mode

Oscillator design for high efficiency DC-DC of micro direct methanol fuel cell

This paper develops a novel oscillator with wide output frequency range, continuous frequency adoption, anti-electromagnetic interference (EMI), and high precision in order to achieve the high energy conversion efficiency of DC-DC for micro direct methanol fuel cell (μDMFC). The oscillator employs the state of art including frequency jitter, slope compensation, and digital trimming to perform the load mode control and detection module, thus linearly adjusting the operating frequency and modulation according to the load. Based on the 0.18 μm microelectronics process, the transient output of the presented oscillator during continuously turning on exports a stable voltage square wave. The jitter frequency ranges only about −1.66% to +4.3% of the base frequency. Moreover, the oscillator can adjust the typical output frequency linearly from 100 kHz to 1 MHz continuously based on the light or heavy load state. The oscillator yields stable performance under EMI with the jittering rate ranges from −31.82% to 36.2%. The quantitative results validates the wide frequency range, continuous frequency adoption, anti-EMI, and high precision of the oscillator. The oscillator solves the low energy conversion efficiency of the μDMFC DC-DC. The oscillator will achieve high energy conversion efficiency and stable output voltage of μDMFC for practical application.

Advancing Stepped-Waveform Radar Jamming Techniques for Robust False-Target Generation against LFM-CFAR Systems.

This study investigates the utilization of a stepped wave frequency modulation jamming technique in radar systems. The objective is to enhance the effectiveness and robustness of false target jamming in the presence of linear frequency modulation (LFM) radars employing constant false alarm rate (CFAR) detection. The proposed method combines stepped frequency modulation with full pulse delay/sum repeat jamming to enhance resilience against uncertainties in target parameters. Theoretical analysis and simulation experiments are conducted to establish relationships between key jammer parameters, such as frequency slope and power compensation, and performance metrics, like false target distribution and CFAR masking. The results demonstrate that the proposed technique effectively maintains a dense distribution of false targets surrounding the protected target, even in the presence of uncertainties in position and signal-to-noise ratio. In comparison to existing methods, the utilization of stepped-waveform modulation enables improved control over target distribution and CFAR masking. Adaptive power allocation compensates for parameter errors, thereby enhancing robustness. Simulation results reveal that the proposed approach significantly reduces the probability of detecting the true target by over 95% under uncertain conditions, while previous methods experienced degradation. The integration of stepped waveforms optimizes false target jamming, thereby advancing electronic warfare capabilities in countering advanced radar threats. This study establishes design principles for resilient jamming architectures and supports enhanced survivability against radars employing pulse compression and CFAR detection. Moreover, the concepts proposed in this study have the potential for extension to emerging radar waveforms.

Microcontroller-Based Trapezoidal Slope Compensation Technique for Peak Current Mode Control at MHz Frequencies

Slope compensation is necessary for the peak cur-rent mode control technique to ensure the stability of the power converter. Micro-controllers (μCs) existing in the market implement the slope compensation using built-in digital to analog converters (DACs). DACs exhibit finite transient times, which can be negligible when the μCs are used to control the power converters at switching frequencies in the order of a few hundreds of kHz. However, for high device switching frequency (HDSF) operation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\geq 1\, \rm{MHz}$</tex-math></inline-formula> ), the DAC transient time becomes significant and can make it difficult, if not impossible, to achieve the conventional ramp slope compensation. Hence, in this paper, a novel concept of ‘trapezoidal’ slope compensation is proposed by considering the transient time of the μC. A detailed analysis is performed to understand the effect of the transient period on the converter stability. The proposed technique is validated with an experimental prototype of 400 W at 1 MHz switching frequency and it is shown to ensure stability of the converter at all operating points within the specification.

Design of Stable Digital V2 Controllers for the Synchronous Noninverting Buck–Boost Converter

The non-inverting buck-boost converter is suitable for battery powered applications as it can operate in buck, buck-boost, and boost modes. Traditional current mode and voltage mode controllers are generally employed to control it in closed loop. It is well established that a peak V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller provides superior load-transient performance compared to conventional current mode and voltage mode controllers. However, a peak V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller cannot be applied to the non-inverting buck-boost converter during boost and buck-boost modes because of its non-minimum phase behavior. This paper proposes a digital peak V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller which can work effectively during all the modes. The proposed controller samples both the inductor current and output voltage at the rate of the switching frequency. Thus, digital implementation of this controller does not need high-speed ADCs. Unlike traditional peak V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controllers, the proposed controller does not depend on effective series resistance (ESR) of the output capacitor. An average model-based small-signal model of the proposed controller is presented. Analysis shows that a sufficient current loop gain can make the system behave like a first order system. This enables the designer to employ a PI controller to achieve superior transient performance in all the modes. Furthermore, fast-scale stability analysis of the controller is carried out using approximate discrete-time models to derive an analytical stability boundary of slope compensation. A non-inverting buck-boost converter prototype is fabricated and the proposed controller is implemented using an FPGA platform. Experimental results show close correlation with the analysis.

Condition for Suppressing Subharmonic Oscillation in Digital Peak Current-Mode Multi-Cycle Controlled Converters

Peak current-mode control is a control algorithm for switched-mode power supplies (SMPSs) that is characterized by high-speed response and high-stability. Currently, a method of implementing peak current-mode control in a digital controller has been proposed however, there is a limit to increasing the switching frequency. Therefore, in a previous study, we proposed a method that enables high-frequency switching by applying a control method called multi-cycle control, which applies the same ON duty ratio over multiple switching cycles to the existing method. Furthermore, in peak current-mode control, an unstable phenomenon called subharmonic oscillation occurs, which is problematic. Generally, this problem is solved by slope compensation however, it cannot be applied to multi-cycle control. Therefore, in previous work, we derived the condition to suppress subharmonic oscillation by designing parameters of multi-cycle control. In this study, we verified the above-mentioned conditions using a real-circuit.

An Adaptive Slope Compensation Circuit for Peak Current Mode of Boost Switching Power Supply

An Adaptive Slope Compensation Circuit for Peak Current Mode of Boost Switching Power Supply

Capacitive Feedbacked Cold-Phase Compensator Analog Pre-Distorter and PAE Enhancer for K-Band CMOS PAs

A K-band two-stage power amplifier (PA) with capacitive-feedbacked cold-phase compensator (cold-PC) linearizer and power-added-efficiency (PAE) enhancer is introduced in 180-nm CMOS technology. This cold-PC consists of two parts. First, a cold-FET analog pre-distorter (APD) with a new capacitive-feedbacked technique is proposed to improve the linear behavior of the PA by enhancing the corresponding APD’s compensation slope. The proposed implementation has a reduced insertion loss and a minimal chip area overhead. Second, a low-pass two-tunable inductive and capacitive PC is proposed to solve the phase shift problem at intermediate nodes that would enhance the PAE of the stacked-transistors configuration. The implemented PA achieves, at 23.5-GHz, a maximum measured PAE of 21.2%, output power at the 1-dB compression point (OP1dB) of 13.4-dBm, and saturated output power of 15-dBm using a total chip area of 0.58 mm2. Employing the proposed cold-PC results in a decrease of the measured error vector magnitude (EVM) of the 400-MHz 5G-NR of 64-QAM modulated signal and an increase of the OP1dB and its PAE by 2.5-dB and 7%, respectively (enhancement by 78% and 72% from the original case, respectively), which, to the best of authors’ knowledge, is the highest reported enhancement of the linearizers of k-band PAs.

A Current-Mode DC–DC Buck Converter With Accurate Current Limit Using Multiplex PWM Comparator

In a conventional current-mode dc–dc buck converter, two sensed inductor current signals are processed in three separate comparators to regulate the converter under various load conditions. These independent sensing currents and comparators not only consume large quiescent current and silicon areas but also cannot guarantee the accuracy of the current limit threshold. This article proposes a current-mode dc–dc buck converter with an accurate current limit using a multiplex pulsewidth modulation (PWM) comparator. Through a multiplex PWM comparator, only one sensing current and one comparator are required to process the inductor current information and complete the regulation of the converter under various load conditions. The response speed of overcurrent protection is also increased without consuming more power and silicon area. Moreover, by generating the zero temperature coefficient (ZTC) sensing current and adding ZTC reference current with slope compensation information, the accuracy of the current limit threshold is greatly improved under various temperatures in a wide input voltage range. The proposed buck converter with a multiplex PWM comparator was fabricated using a standard 1P3M 0.18 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m BCD (BiCMOS/DMOS) process and the experimental results show that the proposed scheme functions properly in the 5-A load range, and the current limit threshold also varies only 8.1% in the temperature range from −40 to 125 °C with the input voltage up to 60 V.

A Wide-Stable-Region Logarithm-Type Slope Compensation for Peak-Current-Mode Controlled Boost Converter

When a peak-current-mode controlled (PCMC) boost converter operates at <inline-formula> <tex-math notation="LaTeX">$D&gt;0.5$ </tex-math></inline-formula>, instabilities such as bifurcations and chaos severely restrict its operation range. This brief proposed a logarithm-type slope compensation (LTSC) to use small amplitude signal to provide enough compensations. Firstly, with the aim of minimizing the error magnification of the input current, the proposed LTSC is deduced. Secondly, the comparisons between the proposed LTSC and other slope compensation (SC) methods are made. Finally, simulations and experiments are carried out to verify the theoretical analysis. The research offered a novel SC to suppress instabilities in PCMC boost converter when <inline-formula> <tex-math notation="LaTeX">$D&gt;0.5$ </tex-math></inline-formula>. The proposed LTSC has advantages such as: (1) LTSC uses smaller amplitude to stabilize the converter; (2) LTSC extend the stable region of boost converter; (3) LTSC can be applied in other PCMC dc-dc converters.

A valley-sensed emulated peak current controlled buck converter for automotive applications

This paper presents an emulated peak current-mode control topology targeted for a high voltage buck converter for automotive applications, where one of the key challenges is to protect the devices from the high voltage stress. The proposed controller scheme eliminates the issue of the voltage stress and at the same time reduces the design complexity of the current sensing block. In addition to that, the inherent issue of sub-harmonic oscillations in the current-mode controller has been resolved by the proposed adaptive slope compensation. The input operating voltage of the converter ranges from 5 V to 36 V with output of 3.3 V. The proposed controller, designed in TSMC 180-nm Bipolar-CMOS-DMOS (BCD) process achieves a minimum on-time of 28 ns and a minimum off-time of 120 ns. It can drive a maximum load of 3.3 A while operating at a switching frequency of 2.1 MHz. The peak power efficiency, achieved at 2 A load, is 93.63%.

Open-Circuit Fault-Tolerant Strategy for Interleaved Boost Converters via Filippov Method

Interleaved converters use an increased number of power electronics switches; this may subsequently affect their reliability. However, this is an opportunity to develop fault-tolerant strategies to improve their reliability and to ensure continuity of service. This is why we herein propose, for the first time, a mathematical function to simultaneously model the healthy and faulty conditions of each switch, thus enabling a unique model of the system. This model is then used in an original fault-tolerant strategy based upon the peak current control with slope compensation. This method not only extends the stable range of the load variation but also ensures the stability in faulty conditions. Finally, the simulation results validate its effectiveness and confirm the theoretical analysis.

Hybrid-Mode PFM Control for LLC Resonant Converter

This article presents a new hybrid-mode pulse-frequency-modulation control method for an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> resonant converter. In the proposed control method, the primary-side resonant current sensing signal of the current-mode control variable is combined with a ramp signal of the voltage-mode control variable to determine an operating frequency. Then, the proposed control method mainly modulates the ramp signal in accordance with the output load condition. Therefore, the control-to-output voltage transfer function has both the current <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</b> mode control and voltage-mode control characteristics that provide fast frequency response and stable output voltage regulation in a light-load condition. In addition, since the ramp signal is also used for slope compensation of the resonant current sensing signal, an external slope compensation circuit is not required. A small-signal ac modeling and loop analysis of the proposed method verify the advantages. The proposed control method is implemented into a field programmable gate array (FPGA) board with an analog front-end board. An experiment is carried out on a 288-W <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> resonant converter. The result shows that the proposed control method provides fast dynamic performance and stable operation under a light-load condition without an additional slope compensation circuit.

Digital peak current mode control of isolated current‐fed push‐pull DC‐DC converter with slope compensation

AbstractThe isolated current‐fed push‐pull dc‐dc converter has some practical advantages such as improved cross regulation characteristics, reduced output noise, and good overall efficiency. Although detailed insight on this converter is available in the literature, the use of digital peak current mode with slope compensation control methodology has not been explicitly presented. This paper discusses digital peak current mode control of a current‐fed push‐pull converter with a novel double digital pulse‐by‐pulse current limiting scheme. Push‐pull topology is implemented on the primary side of an isolation transformer in a dc‐dc bidirectional converter. Achieving this control solution of isolated push‐pull converter is attractive especially in controlling battery power flow in smart micro‐grids. By using a digitally controlled push‐pull converter, the ability to change controller parameters and the use of droop control methods for storage are easier. Furthermore, current mode control provides capability of equal current sharing between parallel converters and eliminates the transformer saturation problem that is common in push‐pull topology. Using continuous time model of the converter, a Type II compensator is designed and implemented in discrete time domain. Digital slope compensation is applied to eliminate the high frequency oscillations caused by current feedback loop. The control method and slope compensation are implemented on STM32F303 mixed‐signal microcontroller. On‐chip analog comparator disabled the PWM output if the sensed current exceeds the reference current until next PWM cycle. The digital controller performance is confirmed by 13 W hardware implementation including fast transient response and stable operation.

A multi-octave microwave 6-bit true time delay with low amplitude and delay variation in 65 nm CMOS

AbstractIn this paper, we describe the design, layout, and performance of a 6-bit TTD (true time delay) chip operating over the entire band of 2–18 GHz. The 1.15 mm2 chip is implemented using TSMC foundry 65 nm technology. The least significant bit is 1 ps. The design is based on the concept of all-pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. A peaking buffer amplifier between bit 4 and bit 5 is used for impedance matching and partial compensation of the insertion loss slope. The rms delay error of the TTD is &lt;1 ps over most of the frequency band and insertion loss is between 2.5 and 6.3 dB for all 64 states.

Fast-Scale Instability and Stabilization by Adaptive Slope Compensation of a PV-Fed Differential Boost Inverter

Numerical simulations reveal that a single-stage differential boost AC module supplied from a PV module under an Maximum Power Point Tracking (MPPT) control at the input DC port and with current synchronization at the AC grid port might exhibit bifurcation phenomena under some weather conditions leading to subharmonic oscillation at the fast-switching scale. This paper will use discrete-time approach to characterize such behavior and to identify the onset of fast-scale instability. Slope compensation is used in the inner current loop to improve the stability of the system. The compensation slope values needed to guarantee stability for the full range of operating duty cycle and leading to an optimal deadbeat response are determined. The validity of the followed procedures is finally validated by a numerical simulations performed on a detailed circuit-level switched model of the AC module.