Slave Module Research Articles

Multiple Human Tracking and Identification With Wireless Distributed Pyroelectric Sensor Systems

This paper presents a wireless distributed pyroelectric sensor system for tracking and identifying multiple humans based on their body heat radiation. This study aims to make pyroelectric sensors a low-cost alternative to infrared video sensors in thermal gait biometric applications. In this system, the sensor field of view (FOV) is specifically modulated with Fresnel lens arrays for functionality of tracking or identification, and the sensor deployment is chosen to facilitate the process of data-object-association. An Expectation-Maximization-Bayesian tracking scheme is proposed and implemented among slave, master, and host modules of a prototype system. Information fusion schemes are developed to improve the system identification performance for both individuals and multiple subjects. The fusion of thermal gait biometric information measured by multiple nodes is tested at four levels: sample, feature, score, and decision. Experimentally, the prototype system is able to simultaneously track two individuals in both follow-up and crossover scenarios with average tracking errors less than 0.5 m. The experimental results also demonstrate system's potential to be a reliable biometric system for the verification/identification of a small group of human subjects. The developed wireless distributed infrared sensor system can run as a standalone prisoner/patient monitoring system under any illumination conditions, as well as a complement for conventional video and audio human tracking and identification systems.

Distributed Kinematic Motion Control of Multi-Robot Coordination Subject to Physical Constraints

This paper presents a kinematic motion control strategy for an n-axle Compliant Framed Modular wheeled Mobile Robot (CFMMR). This robot is essentially a passive-joint active-wheel snake robot where coordinated motion of the robot modules is critical for maximizing mobility and minimizing traction forces. A distributed master—slave kinematic motion control structure is proposed where the front axle module of the robot is the master and subsequent axle modules are slaves. An existing path manifold based controller is used to guide the motion of the master. Two steering algorithms with different specializations are then proposed for the slave modules. Performance of the steering algorithms is characterized based upon their capability to reduce traction forces, control final robot posture, and maneuver in a limited space. It is shown that these algorithms satisfy the physical constraints of the robot, which are characterized by path curvature and velocity limitations. Simulation and experimental results validate and characterize the performance of the algorithms.

A high-speed optical multi-drop bus for computer interconnections

Buses have historically provided a flexible communications structure in computer systems. However, signal integrity constraints of high-speed electronics have made multi-drop electrical buses infeasible. Instead, we propose an optical data bus for computer interconnections. It has two sets of optical waveguides, one as a fan-out and the other as a fan-in, that are used to interconnect different modules attached to the bus. A master module transmits optical signals which are received by all the slave modules attached to the bus. Each slave module in turn sends data back on the bus to the master module. Arrays of lasers, photodetectors, waveguides, microlenses, beamsplitters, and Tx/Rx integrated circuits are used to realize the optical data bus. With 1 mW of laser power, we are able to interconnect eight different modules at 10 Gb/s per channel. An aggregate bandwidth of over 25 GB/s is achievable with 10-bit wide signaling paths.

A 4-W Master–Slave Switching Amplitude Modulator for Class-E1 EDGE Polar Transmitters

For Class-E1 EDGE polar transmitters, we proposed a 4-W master-slave switching amplitude modulator (MS-SAM) for both high efficiency and wide bandwidth. It consists of a combination of two step-down modules with different switching frequencies and different switch sizes. The master module was designed for wide bandwidth and the slave module for high efficiency. The paper also presents a new current-sensing circuit based on a sample-and-hold circuit operable under a high switching frequency (40 MHz). We showed the topologies and operating principles. The chip was fabricated in a standard 0.35-m CMOS process with an area of 6.45 mm . The MS-SAM could drive the amplifiers of up to 4-W RF power in the experiment. We obtained an efficiency of 89%, and the converter's bandwidth was wide enough to meet the EDGE spectral requirements.

Master–Slave Current-Sharing Control of a Parallel DC–DC Converter System Over an RF Communication Interface

Using analog wireless communication, we demonstrate a master-slave load-sharing control of a parallel dc-dc buck converter system, thereby eliminating the need for physical connection to distribute the control signal among the converter modules. The current reference for the slave modules is provided by the master module using radio-frequency (RF) transmission, thereby ensuring even sharing of the load current. The effect of delay due to RF transmission on system stability and performance is analyzed, and regions of operation for a stable as well as satisfactory performance are determined. We experimentally demonstrate a satisfactory performance of the master-slave converter at 20-kHz switching frequency under steady state as well as transient conditions in the presence of a transmission delay. The proposed control concept, which can potentially attain redundancy that is achievable using a droop method, may lead to more robust and reconfigurable control implementation of distributed converters and power systems. It may also be used as a (fault-tolerant) backup for wire-based control of parallel/distributed converters.

Development of the Optical Multiplexer Board Prototype for Data Acquisition in the TileCal System

This paper describes the development of the optical multiplexer board (OMB), also known as PreROD board, for the TileCal readout system in the ATLAS experiment. The aim of this board is to overcome the problems that may arise in the integrity of data due to radiation effects. The solution adopted has been to add redundancy to data transmission and so two optical fibers with the same data come out from the detector front end boards. The OMB has to decide in real time which fiber, eventually, carries data with no errors switching it to the output link connected to the read out driver (ROD) motherboard where data processing takes place. Besides, the board may be also used as a data injector for testing purposes of the ROD motherboard. The paper describes the design and tests of the first prototype, implemented as a 6U VME64x slave module, including both hardware aspects, focusing on signal integrity problems, and firmware aspects, dealing with the cyclic redundancy code algorithms used to check data consistency used to make the decision

Low-Cost Visual Sensor Node for BlueTooth-Based Measurement Networks

This paper proposes a wireless visual sensor comprising of a low-cost grayscale camera as the sensing hardware and a BlueTooth (BT) 100-m slave module as the transmission hardware. The latter enables the sensor to be inserted as a node in a medium-range BT measurement network. The proposed sensor, which is designed to satisfy precise specifications in terms of image-transfer rate and power consumption, represents a good image-acquisition solution in a wide range of applications where hardwiring between camera and image processor is undesired. This paper describes the hardware used and the overall operating principle behind the sensor, discusses the sensor-node performance, and reports the results of reliability tests.

Wireless PWM Control of a Parallel DC–DC Buck Converter

We demonstrate a new concept for wireless pulse-width modulation (PWM) control of a parallel dc-dc buck converter. It eliminates the need for multiple physical connections of gating/PWM signals among the distributed converter modules. The new scheme relies on radio-frequency (RF) based communication of the PWM control signals from a master to the slave modules. We analyze the system stability and demonstrate the experimental effectiveness of the wireless control scheme for a two-module parallel buck converter for 10-kHz and 20-kHz switching frequencies and for channel lengths of 1.5 and 15ft, respectively. The proposed control concept may lead to easier distributed control implementation of parallel dc-dc converters and distributed power systems, and may lead to redundancy that is achievable using droop method. It may also be used as a backup for wire-based control of parallel converters to provide fault tolerance.

Low-power hybrid wireless network for monitoring infant incubators

We have created a pilot wireless network for the convenient monitoring of temperature and humidity of infant incubators. This system combines infrared and radio frequency (RF) communication in order to minimize the power consumption of slave devices, and we therefore call it a hybrid wireless network. The slave module installed in the infant incubator receives the calling signal from the host with an infrared receiver, and sends temperature and humidity data to the host with an RF transmitter. The power consumption of the host system is not critical, and hence it uses the maximum power of infrared transmission and continuously operating RF receiver. In our test implementation, we included four slave devices. The PC calls each slave device every second and then waits for 6 s, resulting in a total scan period of 10 s. Slave devices receive the calling signals and transmit three data values (temperature, moisture, and skin temperature); their power demand is 1 mW, and can run for about 1000 h on four AA-size nickel-hydride batteries.

Distributed Path-Based Inference in Semantic Networks

This paper presents the task model, instruction set, reasoning scheme, software infrastructure, as well as the experimental results, of a new distributed semantic network system. Unlike the synchronous and static marker passing algorithm previously used for parallel semantic network design, our system operates asynchronously, supporting knowledge sharing, dynamic load balancing and duplicate checking. To better the performance in distributed environments, the system has two collaborating components: the slave module, which performs task executions and the host module, which interacts with the user and processes the information for the slaves. Our current implementation focuses on path-based knowledge inferences, using ANSI C and the MPICH-G2 with flex lexical analyzer and the yacc parser generator. Tests of individual components have been performed on a SUN multiprocessor server. The experiments demonstrate promising speedups.

Current limitation control for multi-module parallel operation of UPS inverters

A current limitation control technique for multi-module parallel UPS inverters is presented. All inverter modules have voltage and current control loops. However, only the voltage loop of the master module is active. The current command of the master module is generated by its voltage controller. Voltage loops of all slave modules are idling. The slave module is only for sharing load current with its current command generated from the previous module. By limiting the output current command of each module and sending the difference between the limited and unlimited current commands to the next module, each module only has to share the load current not completely provided by all previous modules. Through circular chain connection of the modules, the number of control interconnections can be minimised. The master module can also be switched online with negligible disturbance for voltage regulation. As only one voltage loop is active at any time, the proposed method is the most stable one when compared with other methods with control interconnection. A robust controller for maintaining good voltage regulating performance even when the parallel number of modules has a large change is also proposed. Three 1 kVA modules have been implemented. The effectiveness of the proposed technique is confirmed with some simulation and experimental results.

A modular and scalable architecture for PC-based real-time vision systems

PC-based real-time vision systems are becoming a de facto standard in industrial applications. They are composed of an illumination system, an image acquisition system and a processing system. In this article, a modular and scalable architecture for real-time vision systems is proposed. On the one hand, we define an acquisition module that allows simultaneous acquisition of up to three monochrome cameras. The acquisition system can be scaled by adding more acquisition modules. The architecture allows simultaneous acquisition of all the modules. On the other hand, we define a processing system composed of different modules and sub-modules which specialize in a particular task: the master module interacts with the external systems; the slave module interacts with the acquisition system and manages the results of its processing sub-modules; each processing sub-module processes the information provided by one single camera. Scalability is provided by increasing the number of slave modules and processing sub-modules that compose the complete vision system. Fast real-time applications can be achieved by assigning one processor per processing sub-module. In this case, multiple PC can be used. Inter-computer communication among modules is carried out by means of sockets (following a master–slave design pattern); intra-computer communication is carried out by means of pipes, shared memory and events. We emphasize herein some real-time considerations related to the multi-processor architecture and the multitasking operating system that allow the implementation of the proposed architecture for real-time vision systems applications. An implementation of this architecture is exemplified with an application successfully installed in a manufacturing company.

Test results of a bi-directional thermodiode system for solar energy utilization

An experimental study was carried out to investigate the heat transfer characteristics of a new bi-directional thermodiode design. The thermodiode was made up of several rectangular loops filled with a fluid and mounted between two vertical plates. Rotatable joints between the horizontal and inclined segments of the loops enable easy alteration of the direction of heat transfer. The dimensions of the loops were optimized for solar heating application. Both master and slave modules were constructed and went through a series of indoor and outdoor tests. Indoor test results showed an onset time of about 15 min for natural convection to be induced throughout the loops when the thermodiode was forward-biased and subject to radiation from 400 to 800 W/m 2. A large temperature difference was maintained across the thermodiode and the cold-end temperature remained almost unchanged during heating when the diode was reverse-biased. In the outdoor tests the throughflow was induced after 90 min of heating in the morning. The maximum temperature difference between the test cells with and without thermodiodes was about 10°C which occurred around noon.

A remote control system for FPGA-embedded modules in radiation environments

A remote control system has been developed for versa module Eurocard (VME) modules located in a radiation environment. Two new VME modules-the remote controller (RC) and local interface modules-are introduced to mediate between the local host and remote slave modules. These two modules are connected with optical links and the local host can master the remote VME bus to access the slave modules through these intermediate modules. This control system can perform watchdog for field programmable gate array (FPGA)-embedded modules whose configuration data are susceptible to single event upsets (SEUs). The architectural study and first prototyping of this system are discussed.

Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core

An IEEE 1149.5 module test and maintenance (MTM) bus slave module interface core is presented, which is used for direct access from the system bus to the IEEE 1149.1 chip-level or on-chip buses to facilitate hierarchical system test and diagnosis. The hierarchical test methodology also is presented, which is applicable to the system-on-chip environment, All the standard 1149.1 instructions, such as SAMPLE/PRELOAD, EXTEST, BYPASS, and even RUNBIST, can be performed within three 1149.5 read/write-data message cycles. The messages are transmitted between the MTM-bus master module (Ill-module) and the slave module (S-module). We adopt the full test access port control method to activate the 1149.1 boundary-scan paths via the 1149.5 MTM-bus. Our S-module interface circuit implements 16 CORE commands and one read/write-data command. It has been prototyped using a field-programmable gate array chip and implemented by a full-custom chip. Hierarchical test of multiple 1149.1 compatible boards has been experimentally verified.

Parallel-Processing Diagnostic Program for a Transputer-Based Readout System

A parallel-processing program for system-diagnostic purposes was developed for a transputer-based readout system of a silicon vertex detector (SVD). The data-acquisition (DAQ) system for SVD was constructed as a part of research and development work for the BELLE [name of a detector for an asymmetric collider experiment at High Energy Accelerator Research Organization (KEK)] experiment consisting of data scanners (DS), slave memory modules (SMM) and direct memory access master modules (DMM). The DS, SMM and DMM have a transputer as a core processor. Each transputer was linked by a point-to-point connection with transputer serial interfaces (Inmos-link). The DAQ system was equipped with a transputer network system with the Inmos-links. The diagnostic program has the capability to detect malfunctioning readout components. To minimize the processing time during an experiment, the program runs in parallel on each transputer. For this purpose, the program was written using the programming language, occam. With the benefits of its distributed system architecture and without the need for any operating system, the program is compact with high modularity. In this paper, we report the system architecture of this diagnostic program.

A CELT and MCST capable VME slave interface

We report on the development of a VME slave interface for the CLEO III detector implemented in an ALTERA EPM7256 CPLD. This includes the first implementation of the chained block transfer protocol (CELT) and multi-cast cycles (MCST) as defined by the VME-P task group of VIPA. Within VME64 there is no operation that guarantees efficient readout of large blocks of data that are sparsely distributed among a series of slave modules in a VME crate. This has led the VME-P task group of VIPA to specify protocols that enable a master to address many slaves at a single address. Which slave is to drive the data bus is determined by a token passing mechanism that uses the *IACKOUT, *IACKIN daisy chain. This protocol requires no special features from the master besides conformance to VME64. Non-standard features are restricted to the VME slave interface. The CLEO III detector comprises /spl sim/400,000 electronic channels that have to be digitized, sparsified, and stored within 20 /spl mu/s in order to incur less than 2% dead time at an anticipated trigger rate of 1000 Hz. 95% of these channels are accounted for by only two detector subsystems, the silicon microstrip detector (125,000 channels), and the ring imaging Cerenkov detector (RICH) (230,400 channels). The occupancy after sparsification in either of these two detector subsystems is expected to be less than 1%, resulting in event fragments on the order of 10 KBytes each, spread over 4, and 8 VME crates, respectively. We developed a chip set that sparsifies, tags, and stores the incoming digital data on the data boards, and includes a VME slave interface that implements MCST and CELT protocols. In this paper, we briefly describe this chip set and then discuss the VME slave interface in detail.

An integrated high performance FASTBUS slave interface

A high-performance CMOS FASTBUS slave interface ASIC (application specific integrated circuit) supporting all addressing and data transfer modes defined in the IEEE 960-1986 standard is presented. The FASTBUS slave integrated circuit (FASIC) is an interface between the synchronous FASTBUS and a clock synchronous processor/memory bus. It can work stand-alone or together with a 32-b microprocessor. The FASIC is a programmable device, which makes possible its direct use in many different applications. A set of programmable address mapping windows can map FASTBUS addresses to convenient memory addresses and, at the same time, act as address decoding logic. Data rates of 100 Mbyte/s to FASTBUS can be obtained using an internal first-in first-out (FIFO) in the FASIC to buffer data between the two buses during block transfers. Message passing from FASTBUS, to a microprocessor on the slave module is supported. A compact (70-mm*170-mm) FASTBUS slave piggyback subcard interface, including level conversion between emitter-coupled logic (ECL) and transistor-transistor logic (TTL) signal levels, is implemented using surface mount components and the 208-pin FASIC chip. >

Optoelectronic readout for scintillating fiber trackers

The CHORUS experiment, a search for νμ-ντ oscillations, will be performed at the CERN wide band neutrino beam. Scintillating plastic fibers will be used for tracking near the vertex and for measurements of the deflection of tracks in the magnet. The plastic fibers have a diameter of 500 μm, a length of 220 cm. In total more than 1 000 000 of these fibers will be used. They will be grouped together to match the entrance window of the optoelectronical readout chain. This is a three-stage image intensifier chain followed by a charge coupled device (CCD). The arguments for the choice of the CCD and the image intensifiers will be discussed. The readout of the CCD will be performed by a commercial VME image processing module. The digitized raw image is transferred to this slave CPU module, stored in its video memory and then processed.

Application Layer for Bitbus Based Low Cost Technological Network

Effective use of automation resources requires that they are interconnected by a communication system. To interconnected field devices such as sensors, actuators and intelligent process controllers; Fieldbus is used. The main idea of Fieldbus is to replace point to point links from each sensor or actuator to it's controller by a serial communication system. In this article we present the field bus from the application layer point of view. Experimental testbed of system consists of some sensors, actuators and PC machines. As a communication network Intel's Bitbus was chosen. Distributed system is based on the architecture of standard host PC with Master Bitbus controller and many remote slaves Bitbus modules (max 250). Each slave module represents microcontroller i8344 with on board memory RAM, EPROM, serial communication interface RS-485 and 8-bit PC-BUS extension which allows controlling of many standard I/O industrial PC cards. PC operates as an extension of a master node. When compared to other commercial field buses, it is seen that Bitbus is at least near enough the I EC standards requirements. Practical experience performed on experimental system have shown that commercial Bitbus software library is cumbersome and is not well suited for hard real time applications. Therefore new software modules were implemented in order to fulfill distributed real-time constraints. The flexibility of the microcontroller i8344 allows to implement specialized Logical Link Control sublayer and a Application layer.