SiZnSnO Thin Film Transistors Research Articles

Frequency Response Characteristics Depending on the Metal Capping Structure and Length of the Amorphous SiZnSnO Thin Film Transistor

Frequency Response Characteristics Depending on the Metal Capping Structure and Length of the Amorphous SiZnSnO Thin Film Transistor

Influence of sub-band gap density of states on the electrical performance of amorphous SiZnSnO thin film transistor

Fabrication, electrical characterizations and numerical simulations are performed on radio-frequency sputtered amorphous SiZnSnO thin film transistors (TFTs). Experimental transfer curves are compared with numerically simulated results to extract the nature of sub-band gap density of states (DOS) of the amorphous channel materials. Defect states arising due to disorder induced localization of electronic wave functions is considered in the numerical simulation process. The extracted DOS for conduction band tail is found to be roughly two order of magnitude lower than that of the a-Si:H. Moreover, disorder asymmetry is also observed between conduction and valence band tail states. In addition to band tails, Gaussian shallow donor-like states and deep level acceptor-like traps are also taken into consideration. The influence of these defect states on the electrical performance of SiZnSnO TFTs has been investigated in detail. Such studies are useful for fundamental understanding of device physics and further improvement of amorphous SiZnSnO based TFT performance and stability.

Effect of channel thickness on the electrical performance and the stability of amorphous SiZnSnO thin film transistor

The electrical performance and the stability of amorphous SiZnSnO (a-SZTO) thin film transistors (TFTs) were investigated depending on the channel thickness. The channel thickness was changed from 27 nm to 108 nm, systematically. As the channel thickness increased, the threshold voltage (VTH) of a-SZTO shifted to the positive direction, from 2.13 to 4.59 V. The negative bias temperature stress test (NBTS) was measured at −20 V for 120 min to determine the stability of a-SZTO TFTs at 60 °C. The ΔVTH was changed only 2.02 V at 27 nm because of less total trap density in the channel layer. The mechanism of stability change depending on the thickness is explained. Transmission line method (TLM) was also used to find the relation between the total resistance (RTotal) and the channel thickness. As increasing the channel thickness, the contact resistance (RC) increased and sheet resistance (Rsh) decreased. It must be considered the channel thickness of a-SZTO channel layer for the electrical properties and stability. Finally, we made the depletion load type inverter using two transistors of different channel thickness. The achieved voltage gain of the inverter is 21.962 V/V at the VDD = 11 V.

Investigation on trap density depending on Si ratio in amorphous SiZnSnO thin-film transistors

High-performance amorphous SiZnSnO thin-film transistors (a-SZTO TFTs) were fabricated using radio-frequency (RF) magnetron sputtering. The noise spectral density of a-SZTO TFTs measured by using the drain current has been reported, and it was found that is possible to apply the conventional 1/fa theory to the low-frequency noise (LFN) of the a-SZTO TFTs. The LFN characteristics of a-SZTO TFTs can be clearly identified by the correlated number fluctuation-mobility fluctuation model. Based on the noise properties, the interfacial trap density (NT) was decreased from 2.32 × 1019 to 1.33 × 1019 cm−3 eV−1 as increasing Si ratio in a-SZTO TFTs. The electrical characteristics and LFN properties of a-SZTO TFTs varied strongly depending on the Si ratio, mainly because the Si atom can act as an oxygen vacancy suppressor.

Dependency of Si Content on the Performance of Amorphous SiZnSnO Thin Film Transistor Based Logic Circuits for Next-Generation Integrated Circuits

On the ZTO system, Si was found to be considered as an oxygen vacancy suppressor due to Si atom having high bonding strength with oxygen. The a-SZTO thin films fabricated with thin-film transistors showed a tendency of decreasing electrical properties as the Si content increased. In addition, various resistances, such as total resistance (Rt), contact resistance (Rc), and sheet resistance (Rsh) depending on Si content were analyzed using transmission line method. It was also found that Rsh was increased due to suppressing oxygen vacancies by Si atom. Threshold voltage can be controlled through simple adjustment of Si content and a NOT logic circuit is fabricated through this. In the fabricated two NOT logic circuits, high voltage gain of 11.86 and 9.23 was obtained at VDD = 5 V, respectively. In addition, we found that even more complex NAND and NOR logic circuits work just like truth tables. Therefore, logic circuits fabricated according to simple Si content can be applied to next generation integrated circuits.

Mechanism of carrier controllability with metal capping layer on amorphous oxide SiZnSnO semiconductor

The change of electrical performance of amorphous SiZnSnO thin film transistors (a-SZTO TFTs) has been investigated depending on various metal capping layers on the channel layer by causing different contact property. It was confirmed that the change of electrical characteristics was sensitively dependent on the change of the capping layer materials on the same channel layer between the source/drain electrodes. This sensitive change in the electrical characteristics is mainly due to different work function of metal capping layer on the channel layer. The work function of each capping layer material has been analyzed and derived by using Kelvin probe force microscopy and compared with the energy bandgap of the SZTO layer. When the work function of the capping layer is larger than that of the channel layer, electrons are depleted from the channel layer to the capping layer. On the contrary, in the case of using a material having a work function smaller than that of the channel layer, the electrical characteristics were improved because electrons were injected into the channel layer. Based on depletion and injection mechanism caused by different contact barrier between metal capping layer and channel layer, NOT, NAND, and NOR logic circuits have been implemented simply by changing metal capping layer on the channel layer.

Effect of Annealing Temperature on Enhancement of Electrical Performance and Stability of Amorphous SiZnSnO Thin Film Transistors

Amorphous Si doped ZnSnO (a-SZTO) was used to investigate the effect of annealing temperature on variation of the electrical performance and stability of amorphous oxide semiconductors used in thin film transistors. It was observed that by as increasing the annealing temperature, the electrical characteristics such as field-effect mobility (μFE), subthreshold swing, and on-to-off current ratio (Ion/off) were enhanced because while the carrier concentration increased the defect decreased. The devices were annealed at 400, 500, and 600 °C. Transfer curves were obtained at 400 and 500 °C, but at 600 °C, a conductive characteristic were revealed because of increased carrier concentration. The negative bias temperature stress (NBTS) was measured at 600 °C. A gate voltage was applied to the devices − 20 V for 2 h. Threshold voltage shift (ΔVth) was measured to be about 5.6 and 1.59 V at 400 and 500 °C respectively. This enhancement was mainly due in the decrease in defects by annealing. By increasing the annealing temperature, the defect density decreased and stability was enhanced. Transmission line method was used to find the relation between the electrical characteristics and the annealing temperature. The total resistance decreased as the annealing temperature was increased, and showed very good agreement with the results of NBTS. In conclusion, the a-SZTO TFT showed the highest electrical performance as well as excellent stability at the annealing temperature of 500 °C.

Influence of Channel Layer Thickness on the Instability of Amorphous SiZnSnO Thin Film Transistors Under Negative Bias Temperature Stress

In this study, amorphous silicon‐zinc‐tin‐oxide thin film transistors (a‐SZTO TFTs) are fabricated by radio‐frequency magnetron sputtering at room temperature, and the influence of various channel thicknesses on their electrical performance and stability is reported. Under the negative bias temperature stress, the transfer curve exhibits threshold voltage shift in the negative direction and degradation of subthreshold swing. In addition, the hump effect occurs in the thick channel, which is primarily due to an increase in total trap density from 5.0 × 1011 to 3.5 × 1012 cm−2 with an increase in the channel layer thickness from 12 to 72 nm. These results agree well with the increase in the bulk trap density because all a‐SZTO TFTs have the same interface; therefore, the interface trap density is excluded. Thicker SZTO TFTs show the hump effect, as they have more donor‐like states in the shallow level. Furthermore, temperature stress at 300–333 K and the activation energy (Ea) falling rate are calculated for a‐SZTO TFTs. The Ea falling rate decreases from 0.103 to 0.010 eV V−1 with increasing channel thickness. Consequently, an a‐SZTO TFT with a 12‐nm channel layer thickness shows a large Ea falling rate (0.103 eV V−1) and a small threshold voltage shift of 4.74 V without the hump effect and degraded electrical performance.

Enhanced Electrical Performance of SiZnSnO Thin Film Transistor with Thin Metal Layer

Novel structured thin film transistors (TFTs) of amorphous silicon zinc tin oxide (a-SZTO) were designed and fabricated with a thin metal layer between the source and drain electrodes. A SZTO channel was annealed at 500℃. A Ti/Au electrode was used on the SZTO channel. Metals are deposited between the source and drain in this novel structured TFTs. The mobility of the was improved from 14.77 ㎠/Vs to 35.59 ㎠/Vs simply by adopting the novel structure without changing any other processing parameters, such as annealing condition, sputtering power or processing pressure. In addition, stability was improved under the positive bias thermal stress and negative bias thermal stress applied to the novel structured TFTs. Finally, this novel structured TFT was observed to be less affected by back-channel effect.

Effect of Annealing Temperature on the Electrical Performance of SiZnSnO Thin Film Transistors Fabricated by Radio Frequency Magnetron Sputtering

Effect of Annealing Temperature on the Electrical Performance of SiZnSnO Thin Film Transistors Fabricated by Radio Frequency Magnetron Sputtering

High performance of full swing logic inverter using all n-types amorphous ZnSnO and SiZnSnO thin film transistors

A high performance inverter consisting of amorphous zinc-tin-oxide (a-ZTO) thin film transistor (TFT) with enhancement mode and amorphous silicon-zinc-tin-oxide (a-SZTO) TFT with depletion mode has been fabricated by using only n-type metal-oxide thin film transistors. The turn on voltages of ZTO and SZTO TFTs showed positive value of 1.17 V and negative value of −5 V, respectively. High voltage gain of about 25 has been obtained by using implemented inverter with good switching characteristics even with all n-type thin film transistors.

Effect of Annealing Time on Electrical Performance of SiZnSnO Thin Film Transistor Fabricated by RF Magnetron Sputtering

Effect of Annealing Time on Electrical Performance of SiZnSnO Thin Film Transistor Fabricated by RF Magnetron Sputtering

Effect of Sputtering Power on the Change of Total Interfacial Trap States of SiZnSnO Thin Film Transistor

Effect of Sputtering Power on the Change of Total Interfacial Trap States of SiZnSnO Thin Film Transistor

Effect of Wet Annealing on the Device Stability of SiZnSnO Thin Film Transistors

Effect of Wet Annealing on the Device Stability of SiZnSnO Thin Film Transistors

First-principle study of amorphous SiZnSnO thin-film transistor with excellent stability

We find that an incorporation of the small amount of Si in the ZnSnO stabilizes the device performance significantly. Through the first-principle calculation, we find that the formation of O-deficient states is easily suppressed by Si-doping due to the volume shrinkage effect, which leads to the stable device operation. This behavior is consistent with the X-ray photoelectron spectroscopy measured data.