Size Penalty Research Articles

Design and fabrication results of Z-gate layout MOSFETs for radiation hardness integrated circuit

A Z-gate layout MOSFET (ZLT) is expected to reduce the total ionizing dose effects which occur in the shallow trench isolation layer made of oxide. To verify the ZLT’s merit, the ZLT was designed and fabricated with the 0.18 μm standard CMOS technology. The ZLT was irradiated with 60Co γ-rays up to 10 Mrad, and its I–V characteristic fluctuation was compared with that of a standard straight gate layout MOSFET (SLT). As a result, it was confirmed that the Z-gate can suppress off-current fluctuations by 1/5, on-current fluctuations by 1/2 and threshold voltage fluctuations by 1/6 compared with the SLT. Since the size penalty of the ZLT is small, it is possible to improve the radiation hardness of the CMOS LSI circuit by just replacing SLTs with ZLTs.

Vector Sensor Steering-Dependent Performance in an Underwater Acoustic Communication Field Experiment.

This paper shows the performance resulting from combining vector sensor directional components in an underwater acoustic communication experiment. The objective is to relate performance with transmission direction and range. Receiver structures based on beamforming and passive time-reversal are tested in order to quantify and compare the steerability impact of vector sensor directional components. A shallow water experiment is carried out with a bottom fixed two-axis pressure-gradient vector sensor. A ship suspended acoustic source transmits coherent modulated communication signals at various ranges and from several directions. Results show that one vector sensor can provide an up to 10 times smaller error bit rate than a pressure sensor, favoring communication robustness without size penalty.

Total ionizing dose effect on 2-D array data transfer ICs designed and fabricated by 0.18 μm CMOS technology

Circuits for CMOS two-dimensional (2-D) array data transfer are indispensable for applications such as space and nuclear fields. Issues include being operated with higher speed, lower power, fewer size penalties, and radiation hardness. To meet these requirements, two kinds of CMOS 2-D array data transfer circuits, such as a shift register type and a memory access type, are proposed and fabricated by the standard 0.18 μm CMOS process technology. In both types, 16 μm pitch, 8 × 128 array data transfer operations were realized with a data rate of more than 1 Gb/s. Furthermore, we conducted 60Co γ-ray irradiation experiments on those circuits. The current consumption ratio of the shift register type to the memory access type ranges from 150 to 200% as the dosage increases. The result indicates that the memory access type has better radiation hardness at 1 Gb/s than that of the shift register type.

Size Discount and Size Penalty: Trading Costs in Bond Markets

Size Discount and Size Penalty: Trading Costs in Bond Markets

Size Discount and Size Penalty: Trading Costs in Bond Markets

We show that larger trades incur lower trading costs in government bond markets (“size discount”), but costs increase in trade size after controlling for clients’ identities (“size penalty”). The size discount is driven by the cross-client variation of larger traders obtaining better prices, consistent with theories of trading with imperfect competition. The size penalty, driven by within-client variation, is larger for corporate bonds and during major macroeconomic surprises as well as during COVID-19. These differences are larger among more sophisticated clients, consistent with theories of asymmetric information. We propose a trading model with bilateral bargaining and adverse selection to rationalize the co-existence of the size penalty and discount.

Transmit Efficiency Enhancement Using Over-the-Air Beamforming Phased Array for High PAPR Signals

This article presents a new transmitter phased-array architecture for efficiency-boosting of a transmitter–receiver link for high peak-to-average power ratio (PAPR) signals. The phased array architecture utilizes sequential over-the-air combining of weighted power amplifiers (PAs) to increase the system efficiency without any die area nor antenna size penalties. The transmitted signal is decomposed into a low duty-cycle signal comprising only the signal peaks and a low PAPR signal containing the remaining envelope levels. The two signals are transmitted through different chains, each optimized for a different power level, and recombined over the air at the receiver side. A 5-GHz PA with a fast 2-ns ON/OFF switching time was designed in 0.18- $\mu \text{m}$ CMOS process to demonstrate the efficiency boost technique. For a four-element array configuration, efficiency enhancement of $2.3 \times $ is demonstrated using an 80-MHz MSC9 802.11ac signal with 9-dB PAPR. The transmitter achieves efficiencies of 15% and 13% for 80- and 160-MHz signals, respectively, at the error vector magnitude (EVM) of −32 dB.

A 4K-Input High-Speed Winner-Take-All (WTA) Circuit with Single-Winner Selection for Change-Driven Vision Sensors

Winner-Take-All (WTA) circuits play an important role in applications where a single element must be selected according to its relevance. They have been successfully applied in neural networks and vision sensors. These applications usually require a large number of inputs for the WTA circuit, especially for vision applications where thousands to millions of pixels may compete to be selected. WTA circuits usually exhibit poor response-time scaling with the number of competitors, and most of the current WTA implementations are designed to work with less than 100 inputs. Another problem related to the large number of inputs is the difficulty to select just one winner, since many competitors may have differences below the WTA resolution. In this paper, a WTA circuit is presented that handles more than four thousand inputs, to our best knowledge the hitherto largest WTA, with response times below the microsecond, and with a guaranty of just a single winner selection. This performance is obtained by the combination of a standard analog WTA circuit and a fast digital single-winner selector with almost no size penalty. This WTA circuit has been successfully employed in the fabrication of a Selective Change-Driven Vision Sensor based on 180 nm CMOS technology. Both simulated and experimental results are presented in the paper, showing that a single pixel event can be selected in just 560 ns, and a multipixel pixel event can be processed in 100 μs. Similar results with a conventional approach would require a camera working at more than 1 Mfps for the single-pixel event detection, and 10 kfps for the whole multipixel event to be processed.

Anti-EMI Noise Digital Filter Design for a 60-kW Five-Level SiC Inverter Without Fiber Isolation

Silicon carbide (SiC) power devices are beneficial to the converters in terms of size reduction and efficiency increase. Nevertheless, the fast switching of SiC devices results in more serious electromagnetic interference (EMI) noise issue. Optical fibers based isolation provides a reliable solution to block the EMI noises from the power circuit to the control circuit but with additional cost and size penalty, especially for multilevel converters. This letter aims at the digital filters based solution to suppress the sampling noise caused by EMI without any extra hardware cost. An improved median filter and a novel magnitude bandpass filter are proposed. The design tradeoffs among noises filter capability, delay effect and the computation time have been discussed for proposed filters. The anti-EMI noise function of proposed filters has been experimentally verified in a 60-kW five-level SiC inverter.

Children and Careers: How Family Size Affects Parents\u2019 Labor Market Outcomes in the Long Run

We estimate the effect of family size on various measures of labor market outcomes over the whole career until retirement, using instrumental variables estimation in data from Norwegian administrative registers. Parents’ number of children is instrumented with the sex mix of their first two children. We find that having additional children causes sizable reductions in labor supply for women, which fade as children mature and even turn positive for women without a college degree. Among women with a college degree, there is evidence of persistent and even increasing career penalties of family size. Having additional children reduces these women’s probability of being employed by higher-paying firms, their earnings rank within the employing firm, and their probability of being the top earner at the workplace. Some of the career effects persist long after labor supply is restored. We find no effect of family size on any of men’s labor market outcomes in either the short or long run.

In monkeys making value-based decisions, amygdala neurons are sensitive to cue value as distinct from cue salience.

Neurons in the lateral intraparietal (LIP) area of macaque monkey parietal cortex respond to cues predicting rewards and penalties of variable size in a manner that depends on the motivational salience of the predicted outcome (strong for both large reward and large penalty) rather than on its value (positive for large reward and negative for large penalty). This finding suggests that LIP mediates the capture of attention by salient events and does not encode value in the service of value-based decision making. It leaves open the question whether neurons elsewhere in the brain encode value in the identical task. To resolve this issue, we recorded neuronal activity in the amygdala in the context of the task employed in the LIP study. We found that responses to reward-predicting cues were similar between areas, with the majority of reward-sensitive neurons responding more strongly to cues that predicted large reward than to those that predicted small reward. Responses to penalty-predicting cues were, however, markedly different. In the amygdala, unlike LIP, few neurons were sensitive to penalty size, few penalty-sensitive neurons favored large over small penalty, and the dependence of firing rate on penalty size was negatively correlated with its dependence on reward size. These results indicate that amygdala neurons encoded cue value under circumstances in which LIP neurons exhibited sensitivity to motivational salience. However, the representation of negative value, as reflected in sensitivity to penalty size, was weaker than the representation of positive value, as reflected in sensitivity to reward size.NEW & NOTEWORTHY This is the first study to characterize amygdala neuronal responses to cues predicting rewards and penalties of variable size in monkeys making value-based choices. Manipulating reward and penalty size allowed distinguishing activity dependent on motivational salience from activity dependent on value. This approach revealed in a previous study that neurons of the lateral intraparietal (LIP) area encode motivational salience. Here, it reveals that amygdala neurons encode value. The results establish a sharp functional distinction between the two areas.

A comparative study of c‐shaped, e‐shaped, and u‐slotted patch antennas

AbstractA class of popular linearly polarized slotted antennas are compared with respect to their RF mechanism, radiation mechanism, impedance matching, and cross polarization characteristics for wireless communication frequency band 1.9–2.4 GHz.It is found that C‐shaped and double C‐shaped patch antennas, even though miniaturized, suffer from narrow bandwidth and high cross polarization level, due to its orientation of slot. U‐slotted and E‐shaped patch antennas show high bandwidth with minor penalty in size and cross polarization level. In order to understand the effect of slot on the radiation in these antennas, a novel strategy of looking at the near‐field of these antennas has been presented. These near‐field plots are analyzed to explain certain far‐field radiation characteristics in these antennas such as‐ cross‐pol level. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1746–1757, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26894

SINGLE MACHINE SCHEDULING WITH A LEARNING EFFECT AND A RATE-MODIFYING ACTIVITY

In the paper, single machine scheduling problems with a learning effect and a rate-modifying activity are considered. Under the learning effect, the processing time of a job is a decreasing function of its position in the sequence. The rate-modifying activity is an event that can change the speed of the machine, and hence the processing time of jobs after the activity. The following objective functions are considered: the makespan, the total earliness, tardiness and completion time penalty, and the total earliness, tardiness, due-window starting time and due-window size penalty. Polynomial time algorithms are proposed to optimally solve the problems.

A Novel Approach to 3D Chip Stacking

Designers seeking electronic package miniaturization but lacking the resources to utilize custom ASIC or complex 3D integration approaches can now take advantage of chip stacking technology for integrating a range of devices into small, system-in-package (SiP) structures. A robust, innovative approach, suitable for supporting low- to medium-volume applications, has been developed which avoids the cost and/or size penalties typically encountered using traditional multi-chip packaging techniques. Using bare die and vertical interconnect/interposer structures, this stacking technology permits the design of multi-chip assemblies with either identical or dissimilar die, co-packaged with discrete and/or integrated passive devices. The approach is independent of ASIC foundry process and does not require through-silicon via (TSV) technology, and is therefore well-suited for designs incorporating multiple IC's from different semiconductor processes or manufacturing sources. Relative to system-on-chip (SoC) ASIC implementations, which carry large upfront NRE costs and long development cycles, 3D co-packaging of heterogeneous devices in customized SiP packages offers a proven, cost-effective alternative with greater design flexibility and reduced time to market. This presentation will describe this novel 3D packaging approach, and how it can be used in conjunction with discrete and integrated passive components to address package designs where size, weight, and/or performance are at a premium.

Single machine scheduling with past-sequence-dependent setup times and deteriorating jobs

This paper considers single machine scheduling problems with setup times and deteriorating jobs. The setup times are proportional to the length of the already processed jobs, that is, the setup times are past-sequence-dependent (p-s-d). It is assumed that the job processing times are defined by functions dependent on their starting times. The following objectives are considered: the makespan, the total completion time, and the sum of earliness, tardiness, and due-window starting time and size penalties. We propose polynomial time algorithms to solve these problems.

Drive Topologies for Solar-Powered Aircraft

Solar-powered aircraft require electric drives for the main propulsion system. It is critical that these drives provide both very high efficiency and low mass. This paper discusses the relative merits of different machine topologies based upon maximizing efficiency, taking into account power-electronic losses, motor losses, mass, and size penalties. Laminated machines are usually limited in their efficiency at light load because of their iron losses. This paper shows how, by combining a high pole number with an ultralow loss lamination material, these machines can be more efficient than other more complex arrangements which have been adopted by others. A demonstrator machine has been built and predicted efficiencies have been validated by test. It has then been used to propel a solar plane to over 60000 feet and extend the aircraft flight-endurance world record from 30 to 84 h.

Highly Reliable SRAM Circuit Technology Using FinFETs

This paper introduces a flex-pass-gate SRAM (Flex-PG SRAM), which is a FinFET-based SRAM to enhance both the read and write margins independently. The flip-flop in the Flex-PG SRAM consists of usual FinFETs, while the pass gates consist of double-"independent"-gate FinFETs, i.e., "four-terminal"- (4T-) FinFETs. By optimizing the current drivability in the 4T-FinFET pass gates according to operational conditions of read and write, both the read and write margins are enhanced. TCAD simulations revealed that the Flex-PG SRAM increases the read margin by 71 mV without the cell size penalty and decrease in the write margin, even when its 6σ tolerance is ensured. Also, a fabricated device proved its feasibility.

If-conversion for embedded VLIW architectures

If-conversion refers to a compiler optimisation that eliminates conditional branches by transforming a control flow region into an equivalent set of conditional instructions. VLIW architectures, used in the design of embedded multimedia processors, can support predicated execution with a limited number of conditional instructions or a full predicated ISA. We present in this paper a speculation framework and a set of Single Static Assignment (SSA) transformations to incrementally build if-converted regions on architectures supporting the select model of conditional moves. This framework has been further extended to support a configurable set of predicated instructions and used to explore architectural variants with predicated memory instructions. We implemented this SSA if-conversion algorithm in the Open64 code generator for the ST231 processor. We show an average cycles improvement of 31% without code size penalty.

Flex-pass-gate SRAM for static noise margin enhancement using FinFET-based technology

We propose a flex-pass-gate SRAM (Flex-PG SRAM), which is a FinFET-based SRAM to enhance both the read and write margins independently. The flip-flop in the Flex-PG SRAM consists of usual FinFETs, while its pass gates consist of double-“independent”-gate FinFETs, i.e., “four-terminal”- (4T-) FinFETs. A 4T-FinFET has a variable threshold voltage controlled by the second gate voltage. This function enables the Flex-PG SRAM to optimize the current drivability in the pass gates according to operational conditions of read and write. This results in enhancement of both the read and write margins. TCAD simulations revealed that the Flex-PG SRAM increases the read margin by 71mV without the cell size penalty and decrease in the write margin, even when its 6σ tolerance is ensured. Also, a half-cell experiment proved its feasibility.

Trace-based leakage energy optimisations at link time

Energy-aware compilers are becoming increasingly important for embedded systems due to the need to meet a variety of design constraints on time, code size and power consumption. This paper introduces for the first time a trace-based, link-time compiler framework on binaries for embedded systems and evaluates its potential benefits in supporting energy optimisations, especially those that exploit the interaction between compilers and architecture. We present two algorithms for reducing leakage energy in functional units and data caches, respectively. Both algorithms work uniformly at the granularity of optimisation regions that are formed by the hot traces of a program. Our experimental results using Mediabench benchmarks show that good leakage energy savings can be achieved at the cost of some small performance and code size penalties. Furthermore, by varying the granularity of optimisation regions, which is a tunable parameter, embedded application programmers can make the tradeoffs between energy savings and these associated costs.

Stacked Single Crystal Silicon TFT Cell의 적용에 의한 SRAM 셀의 전기적인 특성에 관한 연구

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is , which is too large compared to of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.