Abstract
If-conversion refers to a compiler optimisation that eliminates conditional branches by transforming a control flow region into an equivalent set of conditional instructions. VLIW architectures, used in the design of embedded multimedia processors, can support predicated execution with a limited number of conditional instructions or a full predicated ISA. We present in this paper a speculation framework and a set of Single Static Assignment (SSA) transformations to incrementally build if-converted regions on architectures supporting the select model of conditional moves. This framework has been further extended to support a configurable set of predicated instructions and used to explore architectural variants with predicated memory instructions. We implemented this SSA if-conversion algorithm in the Open64 code generator for the ST231 processor. We show an average cycles improvement of 31% without code size penalty.
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