Switch Size Research Articles

배합사료와 생사료로 사육한 넙치의 체조성 및 육질 비교 평가

This study was conducted to evaluate the quality characteristics (proximate composition, fatty acids, amino acids and sensory properties) of whole body and dorsal muscle in olive flounder, which is switch size from juvenile to growing fed extruded pellets (EP) and raw fish-based moist pellet (MP) for 9 months. Sample was collected at 5 and 9 months to compare with those of EP and MP. Whole body crude protein of fish fed EP at 9 months was significantly higher than that of fish fed MP (P<0.05). Linolenic acid(18:3) and n-6/n-3 ratio in dorsal muscle of fish fed EP were significantly higher than those of fish fed MP (P<0.05). No significant differences were observed in the results of the flavor, color, taste and texture of the muscle of the fish fed EP compared to those fed MP (P>0.05). Based on the experimental results, we concluded that olive flounder cultured with EP is not inferior to those fed MP for quality characteristics of whole body and muscle.

Optimization of Microring-Based Interconnection by Leveraging the Asymmetric Behaviors of Switching Elements

With the objectives of reducing power consumption, insertion loss, nonuniformity and crosstalk, optimal configurations for optical interconnection are derived, by leveraging the unequal characteristics at bar or cross state of microring switching elements. A novel and efficient heuristic is proposed for finding the optimum switching configuration. It is shown that the optimum average total insertion loss per path using 2 $\,\times\,$ 2 Basic Switching Element (2B-SE) achieves a 3.65-dB improvement for 128 $\,\times\,$ 128 switch size. The optimum average total insertion loss using 2B-SE in the worst-cast path is shown to be 7.2 dB less than the baseline values. Furthermore, for 128 $\,\times\,$ 128 switch size, the minimum improvement is 7.2 dB for the nonuniformity in the worst case, whereas the total crosstalk has a 2.43-dB improvement. The effect of non-uniform switch elements is also studied.

A Miniaturized Millimeter-Wave Standing-Wave Filtering Switch With High P1dB

This paper presents the design considerations of a silicon-based transmit/receive (T/R) switch for microwave and millimeter-wave frequencies. Techniques for minimizing switch size and loss while increasing linearity are discussed. With the dedicated idea of the standing-wave concept, a combo design of a bandpass filter and switch, called the filtering switch, is introduced for the front-end system to achieve better performance in terms of low insertion loss, compact size, and good linearity simultaneously. Based on the proposed switchable artificial resonator, a standing-wave single-pole single-throw (SPST) and a single-pole double-throw (SPDT) filtering switches are designed and implemented for demonstration. Fabricated with a 0.18- $\mu{\hbox {m}}$ SiGe BiCMOS process, the standing-wave SPST exhibits only 1.9-dB insertion loss and 18-dB isolation with a compact chip area of only 0.027 ${\hbox {mm}}^{2}$ at 50 GHz. The SPDT T/R switch exhibits 3.2-dB insertion loss, good stopband rejection, and 20-dB isolation with only 0.0675 ${\hbox {mm}}^{2}$ active chip area at 60 GHz. With the proposed standing-wave topology, a good linearity with the input 1-dB compression point (P1dB) of 21 dBm is obtained for both switches.

Curved in-plane electromechanical relay for low power logic applications

A curved design for in-plane micro- and nano-electromechanical switches based on a single clamped cantilever is proposed, optimized with finite-element simulations and demonstrated experimentally. The design enables precise control of the switch motion and of the closed-state air gap, resulting in a uniform electrostatic field and increased robustness. The switch size and curvature are optimized for actuation voltage, actuation energy and the electrostatic field strength. These optimizations and the proposed fabrication process are amenable to micro- and nano-electromechanical switches. The scalability of the concept is demonstrated with simulations of nanoscale relays in terms of force and energy, showing that the concept is suitable for sub-100 aJ switching energy. Experimental results on microscale devices demonstrate the advantages of the curved MEM switches, namely a fabrication process with a single sacrificial layer for a switch with a low actuation voltage and excellent robustness. The designed as well as the experimentally observed breakdown voltage is four times higher than the contact voltage, thus enabling a large operating window for electromechanical switches.

Scalable and energy-efficient packet switches based on multi-granular forwarding operations

Telecommunication networks are evolving due to rapid growth of internet traffic and the necessity to satisfy the new requirements of emerging packet services. Upgrading of network devices so as they can allow scalable and full line rate traffic aggregation and eliminate any internal performance bottlenecks is crucial. In packet switching devices, since data plane functionalities need to be executed for each incoming packet and power per given bandwidth is strongly related to the amount of processing on this data, packet processing at ultra-high rate is becoming the major challenge. The main trend to address such power consumption and scalability issues is to bypass packet switches by switching traffic at lower layers. This results in the packet optical transport network approach, where packet switching provides flexible end-to-end connectivity based on tunnel encapsulation while wavelength switching, exploiting optical bypass, allows reducing electrical switch size at transit nodes. There are also opportunities consisting in simplifying packet switch functionalities or designing completely different packet switch architectures. In this paper a new Ethernet aggregation and switching solution with potentialities to simplify and scale Ethernet switch forwarding functionality is proposed. This solution, based on a burst-basis transmission compliant with the Ethernet Standard, is able to maintain flexibility and any to any connectivity deriving from the connectionless nature of Ethernet. At the same time, it provides Ethernet technology with efficient aggregation capabilities allowing to reduce processing of transit traffic. This is allowed thanks to an Ethernet burst structure conceived as a variable number of consecutive frames of the same connection preceded by a proprietary burst control frame carrying information necessary for burst data frames classification. As a result, burst control frames experience the conventional Ethernet switch packet processing while data frames are mapped on the corresponding queue/output port according to the result of control frames classification. The proposed solution also provides the possibility to recognize data frames of the same burst through a proprietary inter-frame gap inserted among them; that allows to dynamically adapt burst size to the available bandwidth at transit nodes in order to limit frame delay and jitter and to support intermediate grooming. These features make it a very competitive approach in the context of packet optical transport being able to support dynamic multi-granular switching. The proposed solution has been validated by estimating its efficiency in terms of energy consumption with respect to a commercial packet switch. The impact of burst transmission on packet delay and jitter across ring and mesh networks has been also evaluated through different sets of simulations.

Embedding N × N Crossbar Switches into ILLIAC(N, N − 1) Torus Networks for Optical Interconnection Networks

A focus of research for crossbar switches has been to reduce the number of 2×2 switch elements, each of which not only occupies a relatively large area but also costs a lot when implemented with optical devices. We point out that conventional N×N crossbar switches, where N is the switch size, actually function as (N+1)×(N+1) switches and thus have redundant 2×2 switch elements to be removed. We show that ILLIAC(N,N-1) torus networks, which have a less number of 2×2 switching elements than crossbar switches of an identical switch size, are equivalent to true N×N crossbar switches. We describe in detail how the crossbar switches can be embedded into the equivalent torus networks. We also discuss switch control complexity of the equivalent torus networks and show that it can be reduced to O(1).

Mixed-line-rate optical network design with wavebanding

To cope with ever increasing and more heterogeneous traffic demands, today’s optical backbone networks are expected to support mixed line rates (MLR) over different wavelength channels. MLR networks can be designed to provide flexible rate assignments to low-bit-rate services and high-bit-rate services in a cost-effective manner. But with increasing number of wavelengths in the network, aggregating wavelengths into wavebands can further reduce the network cost.In this study, we incorporate the idea of waveband switching in MLR network design. Wavebanding or grouping of optical paths reduces the optical switch size at the optical cross-connects (OXCs). When several lightpaths share several common links, they can be grouped together and routed as a single waveband. For optical bypass at a transit node, only two optical ports are required for each waveband, hence reducing the port cost. It can be a challenge for an MLR network to waveband wavelengths of different line rates that have different transmission reaches. In our design, we present a suitable switching architecture and propose an efficient and cost-effective approach for wavebanding in an MLR network. The design problem is formulated as a mixed integer linear program (MILP) where the objective is to minimize transponder cost and port cost. A heuristic algorithm for wavebanding in MLR networks is provided. To further optimize our solution, we also present a Simulated Annealing algorithm for wavebanding. Our results show a significant improvement in cost savings compared to single-line-rate (SLR) networks with wavebanding and an MLR network employing only wavelength switching.

Optical Node Architectures That Utilize Dedicated Add/Drop Switches to Realize Colorless, Directionless and Contentionless Capability

This paper proposes optical node architectures for the single-layer optical cross-connect (OXC) and hierarchical OXC (HOXC) that utilize dedicated add/drop switches for originating/terminating traffic at a node. For both single-layer OXC and HOXC, three architectures with different restrictions on add/drop capabilities are presented. The performance of the proposed architectures is compared through numerical experiments. The architectures significantly reduce total switch scale and minimize necessary switch size while attaining colorless, directionless and contentionless capabilities.

畴反转结构片状集成4×4电光开关的设计与仿真

An integrated 4×4 planar electro-optic switch is designed based on the electro-optic effect in ferroelectric inverted domains.It integrated four minute half-parabola shaped and four parabola shaped deflectors with the same configurations in a ferroelectric wafer.To optimize the design of the parabola shaped deflectors,an appropriate electro-optic switch is provided.Its properties of switch and exchange are analyzed using the beam propagation method(BPM).Simulation results show that the 4×4 planar electro-optic switch is feasible and the beam deflection errors can be compensated in practice by adjusting applied electric-field.The size of the optical switch is 48 mm×2.2 mm×0.5 mm and its maximum applied electric-field is about 13.73 V/μm.It has potential applications in high-speed optical exchange systems.

On the necessary and sufficient requirement of a CIOQ switch to emulate an Output Queued switch

There has been much interest to emulate the behavior of Output Queued switches. The early result of such attempts was reported by Prabhakar and McKeown using the CIOQ switches with speedup factor of 4. Subsequently, Stoica and Zhang and independently Chuang et al. showed that a speedup of 2 in conjunction with their scheduling schemes would be sufficient for CIOQ switches to emulate Output Queued switches.Additionally, Chuang et al. showed that in “Average Sense” a speedup of 2−1/N is necessary and sufficient for CIOQ to emulate Output Queued switch behavior.Our paper reports that in the “Strict Sense” a speedup of 2 is both necessary and sufficient. We show this requirement using examples for 2x2 and 3x3 switches. Then, with a constructed traffic pattern, it is proved that in the “Strict Sense” a speedup of 2 is necessary to emulate the behavior of an Output Queued switch for any switch size N.Combining this result with the previous scheduling schemes, we conclude that in the “Strict Sense”, a speedup of 2 is the necessary and sufficient condition to emulate the behavior of an Output Queued switch, using a CIOQ switch.Additionally, easing the assumptions and allowing the packet segmentation, it is shown that the speedup requirement to emulate the behavior of an Output Queued switch can be reduced to values even smaller than 2−1/N. For this case a lower bound of 3/2 and an upper bound of 2 is proved.

Influence of Transmission Impairments on the OSMOSIS HPC Optical Interconnect Architecture

We examine the impact of transmission impairments on the performance of the optical supercomputer interconnect architecture, initially proposed in the context of the optical shared memory supercomputer interconnect system (OSMOSIS) project. We study two versions of the aforementioned optical interconnect that differ in terms of the number of semiconductor optical amplifiers (SOAs) used as ON-OFF gates. For practical reasons related to packet arbitration, the size of the crossbar switch of the optical interconnect in this study is limited to 64 ports. The switch is based on a broadcast-and-select architecture and employs DWDM in conjunction with 10 Gb/s intensity modulation/direct detection per wavelength channel. We show, both by experiment and by simulation, that the minimization of the number of SOAs in the optical switch by taking advantage of the cyclic routing capability of optical arrayed waveguide multiplexers/demultiplexers leads to negligible performance deterioration compared to conventional wavelength-space switches that are prohibitive slower and do not use any inherent gain properties like in OSMOSIS.

Multi-cabinet implementation for Load-Balanced Optical Switch

Load-Balanced Optical Switch (LBOS) [20] ensures close-to-100% throughout and all-optical transmission between linecards. In this paper, we extend LBOS for multi-cabinet implementation. The challenges lie in the fact that the practical implementation requirements in single-cabinet LBOS become un-scalable for multi-cabinet scenario. First of all, we remove the restriction on LBOS that propagation delay ( t p) between adjacent linecards must equal to the transmission time ( t pkt) for sending one packet. The delay t p is relaxed to be any value, which can accommodate the long and unequal distances fibers among cabinets. Secondly, we outstrip the upper bound of switch size N = 160 in LBOS. The basic idea is that the adjacent linecards share an identical channel/wavelength. Then LBOS can be scaled to support the large switch size of multi-cabinet. Last but not least, a more feasible fair scheduler is devised to replace the original one in LBOS. The simulation results show that multi-cabinet LBOS yields a much better delay/throughput performance than other multi-cabinet optical switches (e.g. Fasnet [8]).

Integration of a Monolithic Buck Converter Power IC and Bondwire Inductors With Ferrite Epoxy Glob Cores

In this letter, we report a concept of integrating a monolithic buck converter power IC with in-package bondwire inductors. The power IC containing all switching devices, driver circuitry, and control logic was designed and fabricated with a standard 0.5-μm CMOS process. Mutliturn bondwires with and without ferrite epoxy glob cores are used as the filter inductor in the buck converter. A prototype system-in-package converter with an output voltage and current of 2.5 V and 120 mA was built to operate at frequencies up to 5 MHz. The power level of the prototype buck converter is scalable by increasing the size of the active power switches.

Optimal Packet Scheduling in WDM Optical Switches With Output Buffer and Limited Wavelength Conversion

All-optical packet switching is a promising candidate for future high-speed switching. However, due to the absence of optical random access memory, the traditional Virtual Output Queue (VOQ) based input-queued switches are difficult to implement in the optical domain. In this paper we consider output-buffered optical packet switches. We focus on packet scheduling in an output-buffered optical packet switch with limited-range wavelength conversion, aiming at maximizing throughput and minimizing average queuing delay simultaneously. We show that this problem can be converted to a minimum cost maximum network flow problem. To cope with the high complexity of general network flow algorithms, we present an algorithm that can efficiently find an optimal schedule in O(min{NW,BW}) time, where <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> is the switch size, W is the number of wavelength channels per fiber and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</i> is the length of the longest FDL at the output of the switch. The complexity of the new algorithm asymptotically matches the lower bound of the scheduling problem. We also conduct extensive simulations to test the performance of the proposed scheduling algorithm under different traffic models.

Performance Analysis of Clos-Network Packet Switch with Virtual Output Queues

A three-stage Clos-network switch with input queues is attractive for practical implementation of a large-capacity packet switch. A scheme that configures the first, second, and third stages in that sequence by performing iterative matchings based on random selections is called the staged random scheduling scheme. Despite the usefulness of such a switch, the literature provides no analytical formula that can accurately calculate its throughput. This paper develops a formula to calculate the throughput analysis of the staged random scheduling scheme for one and multiple iterations used in an input-queued Clos-network switch under uniform traffic. This formula can be used to verify simulation models for very large switches. The introduced derivation considers the processes of the selection scheme at each stage of the switch. The derived formula is used in numerical evaluations to show the throughput of large switch sizes. The results show that the staged random scheduling scheme with multiple iterations for a Clos-network switch with VOQs without internal expansion approaches 100% throughput under uniform traffic. Furthermore, evaluations of the derived formulas are used in a practical application to estimate the number of iterations required to achieve 99% throughput for a given switch size. In addition, the staged random scheduling scheme in an input-queued Clos-network switch is modeled and simulated to compare throughput estimations to those obtained with the derived formulas. The simulation results support the correctness of the derived formulas.

Influence of Size and Shape of Switch on Operability in Portable Resistive Touch-Sensitive Screen

Influence of Size and Shape of Switch on Operability in Portable Resistive Touch-Sensitive Screen

Two-stage shared fiber delay line optical packet switch for contention resolution in optical packet-switching network

Packet contention is a major issue in an optical packet-switching network. We focus on contention resolution using fiber delay lines (FDLs), which are used to buffer contended packets in order to forward these packets to the desired output port to some future time slots. Most of the existing optical buffering schemes are output based, which require a huge number of FDLs as well as a larger switch size and incur extra implementation cost. A shared FDL buffering approach is considered to reduce implementation cost. This paper proposes a two-stage shared FDL optical packet switch to resolve contention, where FDLs are implemented in two stages using extremely simple auxiliary switch. The performance of the proposed switch architecture is evaluated through simulation under trivial and bursty traffic condition, in terms of packet loss rate and average delay. Other performance parameters, such as cross-talk, insertion loss, switch time, etc., are also discussed. Simulation result shows that, the packet loss rate of the proposed architecture under heavy traffic load ( = 0.9) is between ~10−3 and ~10−4 for a 32×32 switch using 64 FDLs, and zero packet loss rate achievable with < 0.8.

Optical Router Control Architecture and Contention Resolution Algorithms Capable of Asynchronous, Variable-Length Packet Switching

This paper presents a new optical-label switching (OLS) router control plane controller for multihop asynchronous, variable-length packet switching incorporating fast, fair, and wavelength-aware arbitration. The proposed optical router controller implements efficient unicast/multicast packet contention resolution algorithms and channel scheduling schemes to resolve the data plane switch fabric contention. The paper evaluates the performance of proposed algorithms in a multihop OLS simulation network with self-similar traffic input under various traffic scenarios. The simulation results demonstrate that the proposed algorithms effectively improve the multihop OLS network performance. The hardware-efficient design and implementation of the proposed router controller and major modules are evaluated in terms of the area and delay for various switch sizes on a Xilinx XCV1000E field programmable gate array (FPGA) chip. Finally, this paper experimentally demonstrates the combined unicast and multicast video streaming enabled by the proposed OLS router control techniques over a label switching testbed with edge routers and realistic Ethernet/IP traffic input.

Performance of two-stage shared fiber delay line optical packet switch under bursty traffic

Packet contention is a major issue in an optical packet switching network. It is not a trivial task to resolve contention due to lack of optical RAM technology. This article proposes a two-stage shared fiber delay line (FDL) optical packet switch for contention resolution. In this article, shared FDLs are used to buffer optical packets, in which a pool of buffer memory is shared among all switch output ports. Most of the existing optical buffering schemes are output-based which require a huge number of FDLs as well as a larger switch size that incur extra implementation cost. However, a shared buffering approach is considered in this article in order to reduce implementation cost. In this article, FDLs are implemented in two stages using an extremely simple auxiliary switch. The proposed switch architecture leads to more efficient use of buffer space. The superiority of the proposed switch architecture has been established by means of extensive simulations. The performance of the proposed switch is investigated under bursty traffic. Simulation result shows that the proposed switch can achieve satisfactory performance at the price of a reasonable amount of FDLs. Moreover, the significance of the proposed switch is confirmed by simulation.

SQUID: A Practical 100% Throughput Scheduler for Crosspoint Buffered Switches

Crosspoint buffered switches are emerging as the focus of research in high-speed routers. They have simpler scheduling algorithms and achieve better performance than bufferless crossbar switches. Crosspoint buffered switches have a buffer at each crosspoint. A cell is first delivered to a crosspoint buffer, and then transferred to the output port. With a speedup of 2, a crosspoint buffered switch has previously been proved to provide 100% throughput. In this paper, we propose two 100% throughput scheduling algorithms without speedup for crosspoint buffered switches, called SQUISH and SQUID. We prove that both schemes can achieve 100% throughput for any admissible Bernoulli traffic, with the minimum required crosspoint buffer size being as small as a single cell buffer. Both schemes have a low time complexity of O(log N), where N is the switch size. Simulation results show a delay performance comparable to output-queued switches. We also present a novel queuing model that models crosspoint buffered switches under uniform traffic.