Six-transistor SRAM Cell Research Articles

On the SRAM with comb-shaped nano FETs advancing to 3 nm node and beyond

In this paper, we describe several scaling challenges of SRAM consisting of FinFETs and horizontal Gate-All-Around (GAA) Nano-sheet Field-Effect-Transistors (NshFETs), especially investigations related to Design-Technology Co-Optimization (DTCO). Comb-shaped channel FETs (CombFETs), which integrates the advantages of FinFETs and NshFETs were introduced to a six-transistor (6 T) SRAM cell and the corresponding simulations were established. The results show that compared with both FinFETs and NshFETs, CombFETs have larger the effective channel width or higher current at the same footprint and larger room for improving the mobility mismatch between N/P transistors. Moreover, CombFET SRAM showed ∼55% increase in effective channel width, 15% improvement of read static noise margin, ∼25% write speed gain, 88% read speed gain or 20% decrease in the minimum operating voltage (Vmin).

A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters

A novel loadless four-transistor static random access memory (4T SRAM) cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32 nm technology node that the read static noise margin (SNM) of the proposed cell reaches 138.7% of the six-transistor SRAM cell and that the hold SNM can be acceptable when the gate insulator thickness of the P-type access MOSFETs is made thinner than the N-type driver MOSFETs. The retention current for the proposed cell decreases to 66.7% of the 6TSRAM and the data rate in read increases to 125%.

Performance Assessment of CMOS circuits using III-V on Insulator MOS Transistors

In this work, with the help of extensive technology computer-aided design simulations, we report a comprehensive study of MOSFET based circuit design using ultra-thin body III-V on-insulator (OI) CMOS transistors. We demonstrate the circuit performance of III-V CMOS by combining InAs-OI n-channel and GaAs-OI junction-less p-channel transistors. The performance metrics of different circuits designed using III-V transistors are also compared with III-V/Germanium and Silicon-on-insulator (SOI) based CMOS logic. CMOS inverter circuit designed using III-V/Ge (InAs-OI/GeOI) CMOS shows 51% and 17% reduction in rise and fall time compared to SOI CMOS. The oscillation frequency of the ring oscillator designed using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) CMOS logic is approximately three times and two times higher than SOI based design. The unity-gain bandwidth of the inverting amplifier using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) architecture is 22 times and 9.5 times higher compared to SOI CMOS based circuit. Static noise margin (SNM) of conventional six-transistor (6-T) SRAM cell is also analyzed during hold operation. Due to the poor electrostatic integrity of III-V transistors, degradation in SNM is observed compared to its SOI counterparts. The cascode low noise amplifier (LNA) circuit designed using InAs-OI transistor shows the higher gain and low noise figure at the same operating frequency compared to the SOI transistor-based LNA.

Robust 12T Sram Cell Using 45nm Technology

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry

A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[Formula: see text] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.

Low voltage high speed 8T SRAM cell for ultra-low power applications

The usage of portable devices increasing rapidly in the modern life has led us to focus our attention to increase the performance of the SRAM circuits, especially for low power applications. Basically in six-Transistor (6T) SRAM cell either read or write operation can be performed at a time whereas, in 7T SRAM cell using single ended write operation and single ended read operation both write and read operations will be accomplished simultaneously at a time respectively. When it comes to operate in sub threshold region, single ended read operation will be degraded severely and single ended write operation will be severely degraded in terms of write-ability at lower voltages. To encounter these complications, an eight transistor SRAM cell is proposed. It performs single ended read operation and single ended write operation together even at sub threshold region down to 0.1V with improved read-ability using read assist and improved dynamic write-ability which helps in reducing the consumption of power by attaining a lower data retention voltage point. To reduce the total power consumption in the circuits, two extra access transistors are used in 8T SRAM cell which also helps in reducing the overall delay.

A Novel Six-Transistor SRAM Cell with Low Power Consumption

A Novel Six-Transistor SRAM Cell with Low Power Consumption

Comparison of SOI Versus Bulk FinFET Technologies for 6T-SRAM Voltage Scaling at the 7-/8-nm Node

The electrostatic benefit of using a silicon-on-insulator (SOI) wafer substrate versus a bulk-silicon wafer substrate with optimized supersteep retrograde (SSR) doping for a low-power 7-/8-nm FinFET technology is investigated via 3-D device simulations and a fitted compact model to estimate the manufacturing yield of six-transistor SRAM cells. SOI FinFET technology is projected to provide only slight improvement in performance and minimum cell operating voltage as compared with SSR FinFET technology.

Cell Ratio Tuning for High-Density SRAM Voltage Scaling With Inserted-Oxide FinFETs

A scheme for controllably adjusting transistor drive strength in inserted-oxide FinFET (iFinFET) technology is proposed, to enable cell ratio tuning for a minimally sized six-transistor (6T) SRAM cell. Specifically, one or more of the stacked nanowire channels within an iFinFET can be made to be essentially non-conducting by ion implantation to increase its threshold voltage. Via 3-D device simulations and a calibrated compact $I$ – $V$ model, this scheme is projected to enable more than 0.1 V reduction in minimum cell operating voltage ( $V_{\mathrm {MIN}})$ for a 6T SRAM high-density cell design.

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal–oxide–semiconductor compatibility. As a result, NEM relays have been significantly investigated as highly energy-efficient design solutions. A major shortcoming of NEMs preventing their widespread use is their limited switching endurance. Hence, in order to utilize the low-power advantages of NEM relays, further device, circuit, and architectural techniques are required. In this paper, we introduce the concept of shadow NEM relays, which is a circuit-level technique to leverage the energy efficiency of the NEM relays despite their low switching endurance. This technique creates two virtual ground nodes in a block to allow: 1) a low power mode with functional NEM relays and 2) a normal mode with failed NEM relays. To demonstrate the applicability of this concept, we have applied it to a six-transistor SRAM cell as an illustrative example. We also investigate the applicability of this SRAM cell in field-programmable gate arrays and on-chip caches. Experimental results reveal that shadow NEM relays can reduce the power consumption of SRAM cells by up to 80% while addressing the limited switching endurance of NEM relays.

Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage

Four write stability metrics for the characterization of six-transistor SRAM cells were experimentally evaluated and compared at low supply voltage ( $V_{\mathrm {DD}})$ . A silicon-on-thin-BOX technology with reduced body doping was used to achieve low voltage operation. It was confirmed that both bitline and wordline methods are preferable in that they yield metrics that follow normal distributions, which is practically beneficial for the yield estimation. On the contrary, different from at high $V_{\mathrm {DD}}$ , both write static noise margin from write butterfly curve and write ${N}$ -curve current ( $I_{W})$ exhibit non-normal probability distributions. The origins of the non-normality are analyzed in detail.

Design of a faster 8T SRAM memory cell

This paper discusses the design of read/write assist circuits which are used in a SRAM cell’s design to overcome the cell’s variations. It also explains the variability problems in a SRAM bit-cell and many approaches to address them. The basic operations, SNM concept, and write margin of an SRAM are described theoretically as well as measured in simulation. The write assisted circuit, the Negative Bit-line Voltage Bias scheme, is discussed and implemented at transistor level using a six-transistor (6T) SRAM cell. With the write assisted circuit, the implemented memory array successfully performs a write operation, the condition in which the same operation would fail without the write assisted circuit. During the simulation, this write assisted circuit helps to achieve the negative bias voltage of -70mV on the SRAM’s bit- lines. The cost overhead includes chip area, power consumption and chip area

Variation-Aware Comparative Study of 10-nm GAA Versus FinFET 6-T SRAM Performance and Yield

This paper benchmarks the performance of gate-all-around (GAA) MOSFETs against that of optimized silicon-on-insulator FinFETs at 10-nm gate length. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for both device structures. The yield of six-transistor SRAM cells implemented with these advanced MOSFET structures is then investigated via a calibrated physically based compact model. The GAA MOSFET technology is projected to provide for 0.1 V lower minimum cell operating voltage with reduced cell area.

Evaluation and Control of Break-Even Time of Nonvolatile Static Random Access Memory Based on Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

The energy performance of a nonvolatile static random access memory (NV-SRAM) cell for power gating applications was quantitatively analyzed for the first time using the performance index of break-even time (BET). The NV-SRAM cell is based on spin-transistor architecture using ordinary metal–oxide–semiconductor field-effect transistors (MOSFETs) and spin-transfer-torque magnetic tunnel junctions (STT-MTJs), whose circuit representation of spin-transistor is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The cell is configured with a standard six-transistor SRAM cell and two PS-MOSFETs. The NV-SRAM cell basically has a short BET of submicroseconds. Although the write (store) operation to the STT-MTJs causes an increase in the BET, it can be successfully reduced by the proposed power-aware bias-control for the PS-MOSFETs.

Evaluation and Control of Break-Even Time of Nonvolatile Static Random Access Memory Based on Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

The energy performance of a nonvolatile static random access memory (NV-SRAM) cell for power gating applications was quantitatively analyzed for the first time using the performance index of break-even time (BET). The NV-SRAM cell is based on spin-transistor architecture using ordinary metal–oxide–semiconductor field-effect transistors (MOSFETs) and spin-transfer-torque magnetic tunnel junctions (STT-MTJs), whose circuit representation of spin-transistor is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The cell is configured with a standard six-transistor SRAM cell and two PS-MOSFETs. The NV-SRAM cell basically has a short BET of submicroseconds. Although the write (store) operation to the STT-MTJs causes an increase in the BET, it can be successfully reduced by the proposed power-aware bias-control for the PS-MOSFETs.

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes.

Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared.

Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors

We propose an asymmetric-MOSFET-based six-transistor (6 T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6 T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology.

A High Density and Low Power Cache Based on Novel SRAM Cell

Based on the observation that dynamic occurrence of zeros in the cache access stream and cacheresident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS five-transistor SRAM cell (5T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. Novel 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 17% smaller than a conventional six-transistor SRAM cell using same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during read/write and also the average dynamic energy consumption of new cell is 30% smaller than a six-transistor SRAM cell.

Characterization of a Novel Nine-Transistor SRAM Cell

Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.