Abstract
The electrostatic benefit of using a silicon-on-insulator (SOI) wafer substrate versus a bulk-silicon wafer substrate with optimized supersteep retrograde (SSR) doping for a low-power 7-/8-nm FinFET technology is investigated via 3-D device simulations and a fitted compact model to estimate the manufacturing yield of six-transistor SRAM cells. SOI FinFET technology is projected to provide only slight improvement in performance and minimum cell operating voltage as compared with SSR FinFET technology.
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