SiON Gate Dielectrics Research Articles

Evolution of oxide charge trapping under bias temperature stressing

Transient oxide-charge trapping and detrapping, commonly regarded as a parasitic effect in the interpretation of dynamic bias-temperature stress (BTS) data, may play an important role on the long term reliability of the gate oxide as revealed by recent studies on the SiON and HfO2 gate dielectrics. Specifically, it is found that transient charge trapping (one which relaxes upon removal of the applied electrical stress) is transformed into more permanent trapped charge when the applied electrical cum thermal stress exceeds a certain threshold. Below the threshold, cyclical transient charge trapping and detrapping behavior is observed. The observations imply that the oxide structure may be modified by the applied stress, making it susceptible to permanent defect generation. In addition, it is found that when the transformation of hole trapping occurs under negative-bias temperature stress, a correlated increase of the gate current is always observed, which points to the transformation process being the origin for bulk oxide trap generation. However, when the transformation of electron trapping occurs under positive-bias temperature stress, an increase of the gate current is not always observed. From ab initio simulation, we show that an intrinsic oxide defect – the oxygen vacancy-interstitial (VO−Oi) – could consistently explain the experimental observations. An interesting feature of the VO−Oi defect is that it can exists in various metastable configurations with the interstitial oxygen Oi in different positions around the vacancy VO, corresponding to different trap energy states in the oxide bandgap. This characteristic is able to account for the BTS induced generation of deep-level trapped charges as well as transformation of transient (or shallow) to permanent (or deep) charge trapping.

Effect of body bias on negative bias temperature instability in pMOSFET with SiON gate dielectrics

We evaluated the body bias (Vbs) effect on negative bias temperature instability (NBTI) in pMOSFET devices with various channel lengths and channel dopant concentrations for the first time. We found that additional NBTI degradation starts to occur due to substrate hot holes when Vbs increases, over a certain transition point. This transition point was dependent on both channel length and channel dopant concentration of the devices. In the pMOSFETs with long channel length and high dopant concentration, even small positive Vbs can cause the additional degradation due to large body effect and high initial threshold voltage (Vt), respectively. This observation can resolve the conflicting arguments on whether Vbs enhances NBTI degradation or not.

High Temperature Annealing of the Interface State Component of Negative-Bias Temperature Instability (NBTI) in MOSFET Devices

We have performed negative bias instability (NBTI) measurements on 130 nm channel length Si MOSFETs with SiON gate dielectrics at different temperatures up to 220 °C. Using a pulsed stressiing and pseudo-DC measurements we have focused on the charging and annealing kinetics of only the interface state related component. At temperatures > 180 °C we find clear evidence for a diminution of the growth kinetics suggesting the onset of an annealing effect during interface state generation. We contrast the NBTI data with interface state growth in devices exposed to ionizing radiation. Possible physical mechanisms contributing to the “annealing” effect are discussed and associated with diffusing H2 molecules present in the substrate/gate insulator/polycrystalline Si gate structure.

Impact of gate poly doping and oxide thickness on the N- and PBTI in MOSFETs

We study n- and pMOS devices with 3.2–30nm thick SiON or SiO2 gate dielectrics and n++ or p++ doped polysilicon gates to identify the type and energetic location of defects created through bias temperature stress. The results clearly indicate a dependence of the type of BTS induced defects on the stress polarity and the gate poly doping. If holes are provided from the p++ poly gate and the gate dielectric is sufficiently thin, NBTI-type donor-like defects may occur even under positive bias stress conditions. For devices with sufficiently thick dielectrics or n++ poly gated devices, holes are absent during PBTI stress and acceptor-like defects are created.

A Physical Model for Post-Breakdown Digital Gate Current Noise

We present a new physical model that enables us to reproduce the digital gate current random telegraph noise fluctuations observed in ultrathin SiON dielectrics in the early stages of post-breakdown (BD). Gate current (IG) fluctuations are modeled assuming that some traps in the BD path switch between two unstable configurations, corresponding to neutral and negatively charged O vacancies. The energy levels of the trap considered in simulations here are consistent with the values calculated from atomistic simulations. The model allows one to reproduce accurately the mean and variation in the IG fluctuations observed on 16- and 22-Å-thick SiON gate dielectrics at different gate voltages.

New Insights of BTI Degradation in MOSFETs with SiON Gate Dielectrics

It is widely recognized that recovery during measurement delay seriously misleads the BTI phenomena. We have developed a modified Charge Pumping (MCP) method to measure the interface trap generation under stress with negligible recovery during measurement delay. The method simply extends the inversion level Vinv of the CP pulse to the stress voltage and keeps the duty cycle of Vinv as large as possible, therefore the stress is almost "on" during measurement. For the first time, we developed a diagram representation of CP process and used to the physical analysis for the contribution and exclusion of slow oxide charge contribution in the CP current of this MCP method. Using this MCP method and the fast pulsed Id-Vg method (FPM) we developed in the past, we systematically investigate and compare the NBTI degradation of p-MOSFETs with thermal (TNO) and plasma (PNO) nitrided SiON gate dielectrics with the same nitrogen surface concentration. We also systematically measure the interface trap degradations in four configurations of NBTI and PBTI stresses for both n-MOSFETs and p-MOSFETs. The following results are achieved: (1) The oxide charge induced degradation in TNO SiON devices is several times larger than those in PNO devices under the same stress condition, due to the larger charge moment in the gate dielectrics of the TNO devices. (2)

New Insights of BTI degradation in MOSFETs with SiON Gate Dielectrics

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Atomistic origin of high-quality “novel SiON gate dielectrics”

We have investigated the effect of the oxygen incorporation into SiN films by the first principles calculations. The calculated results show that the oxygen incorporation tends to generate defect states in SiN band gap by forming dangling bonds and floating bonds of Si. Based on the calculated results, it is also indicated that the high quality SiON film can be fabricated by suppressing the incorporation of O atoms into the SiN film, reproducing the reported experiments.

Pulse stress frequency dependence of negative bias temperature instability in SiON gate transistors

Dependence of negative bias temperature instability (NBTI) on the frequency of the pulsed stress applied on p-channel transistors with plasma nitrided SiON gate dielectrics is studied. The threshold voltage shift (ΔVth) decrease is observed with increase in frequency. The fractional relaxation is found to be more remarkable after a pulse stress with higher frequency. A phenomenological model based on the dispersive transport of hydrogen in the gate dielectrics is proposed to explain the pulse based NBTI characteristics. The frequency dependence of NBTI is attributed to the existence of deep level hydrogen traps in the gate dielectrics. The model predicts reduced frequency dependence in the ultrahigh frequency range. The results and discussion also confirm the overall correctness of the dispersive transport framework in interpreting the NBTI mechanisms.

Insights on trap generation and breakdown in ultra thin SiO 2 and SiON dielectrics from low voltage stress-induced leakage current measurements

We review the advancements in the understanding of breakdown and trap generation that have been achieved using low voltage stress-induced leakage current as a probe of the interface states created during electrical stress of ultra thin SiO 2 and SiON gate dielectrics. The technique separates the effects of bulk and interface states on the post-stress I– V characteristics; senses interface traps at both contact interfaces, identifies the regime where interface rather than bulk state generation is the rate limiting step for breakdown, is useful for determining the operative trap creation processes, and reveals the role of trap generation mechanism in driving which stress-induced defect controls breakdown.

The Impact of Stacked Cap Layers on Effective Work Function With HfSiON and SiON Gate Dielectrics

Cap layers have been used to modulate the effective work function (EWF) for high- /metal-gate CMOS devices. We have investigated the impact of stacking cap layers on the EWF. Stacked cap layers consisting of two sequential cap layers, including, Al2O3, Dy2O3, Sc2O3 and La2O3, were formed on HfSiON or SiON as host dielectrics. It is demonstrated that the EWF change due to the stacked cap layers corresponds to the sum of the EWF change from each single cap layer. Furthermore, no host dielectric dependence on the shifts is observed. This behavior is attributed to the complete intermixing of the stacked cap layers with the host dielectrics.

SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics

Negative bias temperature instability (NBTI) and stress-induced leakage current (SILC) both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts: the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress.

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal–oxide–semiconductor field effect transistors–low temperature electron mobility study

We report low temperature (40–300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal–oxide–semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Ultrathin decoupled plasma nitridation SiON gate dielectrics prepared with various rf powers

Decoupled plasma nitridation (DPN) SiON films for short channel complementary metal-oxide-semiconductor (CMOS) devices were prepared with various rf powers. As we increased the SiON deposition power from 200to400W, it was found that gate leakage current increased while gate breakdown voltage decreased. It was also found that the authors can achieve more uniform thickness and nitrogen distributions across the wafers, smaller off-state current, and better Vt rolloff characteristics from the PMOS field-effect transistors (MOSFETs) with 400W DPN SiON films. Furthermore, it was found that they can achieve larger hot carrier injection (HCI) lifetime and better HCI resistance from the NMOSFETs with 400W SiON films. However, it was also found that negative bias temperature instability lifetime of the PMOSFETs with 200W SiON films was longer.

Performance of current mirror with high- k gate dielectrics

This work compares the performance of the basic current mirror topology by using two different materials for gate dielectrics, the conventional SiON and an Hf-based high- k dielectrics. The impact of gate leakage and of channel length modulation on the basic current mirror operation is described. It is shown that in the case of SiON gate dielectrics with an equivalent oxide thickness (EOT) of 1.4 nm, it is not possible to find a value for the channel length which allows a good trade-off to be obtained while minimizing the gate leakage and reducing the channel length modulation. On the other hand, the study demonstrates that in the case of HfSiON gate dielectrics with similar EOT, appropriate L values can be found obtaining very high output impedance current sources with reduced power consumption owing to low leakage and most of all with better parameter predictability.

The Physical Origins of Fast and Slow Components in NBTI Degradation for p-MOS Transistors with SiON Gate Dielectric

We summarize our recent investigation on the NBTI degradation in p-MOSFETs with SiON gate dielectric. (1)For the slow NBTI component, we show evidence that the degradation and recovery is due to interface trap Nit generation and passivation. Nit measured by conventional CP and DCIV methods is underestimated due to passivation under measurement; (2) Due to the degradation during initial threshold voltage measurement, the existing (slow) on-the-fly measurement distorts (overestimates) the slope and induces a kink at early stress time in the Log-Log curve of static NBTI degradation time evolution. A fast on-the-fly method is developed to overcome this problem. (3) An ultra-fast (100ns) transient pulse Vth measurement method is developed to avoid the recovery of fast NBTI component during measurement, and is compared to the fast on-the-fly measurement results with excellent agreement. (4) Our experiments show that there are two NBTI components, fast and slow. The fast component measured by ultra-fast pulsed method is mainly due to trapping de-trapping of oxide charge. All experimental results can be well explained in this scheme with very good quantitative agreement between the modeling and the experimental data.

The Impact of F and N Incorporation Technique on Advanced Gate Stacks

Control of threshold voltage (Vth) is a common and serious problem for realizing scalable LSIs with either nitrogen rich SiON, high-k gate dielectrics, or metal gates. In this paper, we demonstrate the improvement of HfSiON pMISFETs characteristics with the F incorporation technique, which may prove to be a powerful tool for lowering |Vth| in pMISFET with both poly-Si and metal gates. Using F implantation in the channel region prior to HfSiON formation, |Vth| lowering up to ~200mV is obtained without mobility degradation. In the same manner as the F incorporation technique, N incorporation is useful for reducing Vth value in nMISFETs. Furthermore, the impact of F incorporation in HfSiON is investigated in terms of reliability. From a comparison of the F incorporation effect on SiON and HfSiON gate dielectrics, we have proposed a model for the F passivation of defects in both HfSiON and the HfSiON/Si interface.

Mechanism of Static and Dynamic Bias Temperature Instability in p- and n-MOSFETs

The BTI-induced degradation of device performance has been ascribed to interface trap generation (ΔNit) and oxide charge buildup (ΔNot) at or near the SiO2/Si interface. Moreover, it has been widely recognized that degradation under dynamic BTI stressing may differ from that under static stressing. In this paper, our recent studies on BTI are reviewed. First, a modified direct-current current-voltage (DCIV) method is proposed, which can monitor ΔNit and ΔNot separately, and is independent on the measurement temperature. Second, negative BTI in pMOSFETs with ultrathin plasma-nitrided SiON gate dielectrics is systematically studied, as well as the effect of nitrogen concentration, using the modified DCIV method. Third, dynamic BTI with is studied at various stressing configurations. A transient degradation enhancement is observed upon quick gate voltage reversal from the accumulation bias to the inversion bias. Finally, a modified reaction-diffusion model is proposed to consistently explain the observed static and dynamic BTI behavior.

Impact of Positive Charges on NBTI Degradation and Characterization in Ultra-Thin SiON Gate Dielectrics

Impact of positive oxide charges on NBTI degradation and characterization was studied in this work. It was found that the subthreshold swing shifts extracted by Id-Vg characteristic measurements are significantly affected by the gate voltage sweep directions. Further experimental results demonstrate that positive oxide charge is responsible for the observed phenomena, simultaneously providing new evidence for the importance of positive oxide charges in NBTI degradation and recovery. Neutralization (and re-charge) of positive charges during the measurements is considered to have significant influence on NBTI characterization. Our results show that the impact of positive oxide charges on the NBTI degradation and characterization should be taken into consideration seriously.

Dramatic Improvement of Vfb Shift and Gmmax with Ultra-thin and Ultra-low-leakage SiN-based SiON Gate Dielectrics

The understanding of the mechanism of Vfb shift and the improvement of the [N]-Vfb shift relationship are essential for realizing SiON film with superior device performance. By forming the smooth SiN film with high-density N-Si3 structure and suppressing the deterioration of Si-N network due to oxidation, SiON films dramatically improved in terms of the [N]-Vfb shift relationship, with ultra-thin EOT (0.71 nm), ultra-low leakage current (134 A/cm2) and high Gm max (115%), are realized. The middle temperature and low-pressure nitridation and the optimization of oxidation conditions are the keys to forming defect-free perfect Si3N4 and SiON films and to achieving these performances.