SiO2 Tunnel Oxide Research Articles

Effect of blocking and tunnel oxide layers on the charge trapping properties of MIS capacitors with ALD HfO2/Al2O3 nanolaminated films

Electrical and charge trapping properties of HfO2/Al2O3 nanolaminated stacks incorporated in three types of metal-insulator-silicon capacitor structures (without blocking and tunnel oxide layers; with 20 nm Al2O3 as blocking oxide and ∼3 nm Al2O3 or thermal SiO2 as tunnel layer) were investigated. HfO2/Al2O3 stacks exhibit a positive initial oxide charge, and adding of the 3 nm Al2O3 tunnel layer to the capacitor doubles the amount of the positive charge and the density. Using SiO2 as a tunnel layer resulted in a negative initial oxide charge which is interpreted by the effect of dipole formation at the Al2O3/SiO2 interface. Tunnel SiO2 provides lowest density of the interface states at silicon and leakage currents. The insertion of blocking and tunnel oxide layers to the capacitors significantly widens the memory windows; capacitors with a SiO2 tunnel oxide demonstrate largest memory windows.

Analysis of passivation property using thin Al2O3 layer and simulation for realization of high-efficiency TOPCon cell

Conventional p–n junction solar cells exhibit good thermal stability but poor carrier selectivity. The main aim of this study was to achieve improved passivation along with carrier-selective contact for a solar cell having a tunnel oxide passivated contact (TOPCon) structure. To this end, we attempted to optimize the polysilicon (poly-Si) layer deposited on an ultrathin (~1.3 nm) SiO2 tunnel oxide layer to achieve high carrier lifetime and low recombination. We observed the passivation properties under varied thicknesses of the poly-Si layer and the phosphine (PH3) gas flow rate at three different annealing temperatures. Our experimental approach was able to achieve the best passivation properties by use of a moderately thin poly-Si layer. The poly-Si layer thickness was varied from 55 to 113 nm, and the PH3 flow rate was varied from 10 to 80 sccm at three different annealing temperatures in the range of 800–950 °C. The 113-nm-thick poly-Si layer was able to yield an implied open-circuit voltage (i-VOC) of 733 mV along with a very low recombination current density (J0) of 5.2 fA/cm2 at a PH3 flow rate of 40 sccm and post-deposition annealing temperature of 900 °C. A higher annealing temperature resulted in damage to the substrate, which in turn led to poor passivation; hence, optimization of this temperature was necessary. The passivation properties were further improved via the deposition of a thin (10-nm thick) Al2O3 layer on one side (i.e., front side) of the symmetric cell structure. This deposition caused a decrease in J0 to 2.5 fA/cm2 and an increase in i-VOC to 742 mV. These results are attributed to a decrease in the number of interfacial defects, promoted formation of a carrier collector layer, and good field-effect passivation. We performed a simulation study for the realization of a TOPCon solar cell and employed therein the experimentally determined parameters, which yielded highly promising cell results. Our proposed simple and cost-effective approach has high potential for future large-scale production of high-efficiency TOPCon solar cells.

Property Improvement of CTF Memories Utilizing Hybrid Tunnel Oxide

Various hybrid tunnel oxides in both MANOS structure and SONOS structure were examined. Among them, SiO2/ZrO2 hybrid tunnel oxide in charge trap flash memory provides promising programming characteristics compared to those of SiO2 tunnel oxide. However, the relatively higher Fowler–Nordheim tunneling barriers for the hole result in insufficient erasing characteristics. In contrast, Si2– X ON X /ZrO2 hybrid tunnel oxide could be erased to negative ${V}_{\textsf {th}}$ . In addition, the retention behaviors of the hybrid tunnel oxides based on an high temperature storage (HTS) test were superior compared to that of SiO2 tunnel oxide. The cycle characteristics in endurance and HTS of Si2– X ON X /ZrO2 hybrid tunnel oxide were confirmed to be better than those of Si2– X ON X tunnel oxide, which implies that they satisfy real operational conditions. Thus, Si2– X ON X /ZrO2 hybrid tunnel oxide can be a promising candidate for a next-generation tunnel oxide.

Mechanism for crystalline Si surface passivation by the combination of SiO2 tunnel oxide and µc-SiC:H thin film

This work demonstrates that the combination of a wet-chemically grown SiO2 tunnel oxide with a highly-doped microcrystalline silicon carbide layer grown by hot-wire chemical vapor deposition yields an excellent surface passivation for phosphorous-doped crystalline silicon (c-Si) wafers. We find effective minority carrier lifetimes of well above 6 ms by introducing this stack. We investigated its c-Si surface passivation mechanism in a systematic study combined with the comparison to a phosphorous-doped polycrystalline-Si (pc-Si)/SiO2 stack. In both cases, field effect passivation by the n-doping of either the µc-SiC:H or the pc-Si is effective. Hydrogen passivation during µc-SiC:H growth plays an important role for the µc-SiC:H/SiO2 combination, whereas phosphorous in-diffusion into the SiO2 and the c-Si is operative for the surface passivation via the Pc-Si/SiO2 stack. The high transparency and conductivity of the µc-SiC:H layer, a low thermal budget and number of processes needed to form the stack, and the excellent c-Si surface passivation quality are advantageous features of µc-SiC:H/SiO2 that can be beneficial for c-Si solar cells. (© 2016 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim)

Study on nanoparticles embedded multilayer gate dielectric MOS non-volatile memory devices

Here, we present a computational study on stacked multilayer nanoparticles embedded gate dielectric MOS non-volatile memory devices. Two device structures, one with a pure SiO2 tunnel oxide and other with a stacked HfO2-SiO2 tunnel oxide were compared. The Au nanocrystals were assumed embedded in a Si3N4 layer. The electrical parameters of the composite multilayer were evaluated using Maxwell-Garnett theory and virtual crystal approximation. From the WKB approximation, the direct and the Fowler-Nordheim tunnelling currents were evaluated, and subsequently the I-V characteristics and the flatband voltage shifts were also simulated. The flatband shift simulations were compared with recent experimental results.

터널 산화막 두께에 따른 Al2O3/Y2O3/SiO2다층막의 메모리 특성 연구

Conventional SONOS (poly-silicon/oxide/nitride/oxide/silicon) type memory is associated with a retention issue due to the continuous demand for scaled-down devices. In this study, Al₂O3/Y₂O₃/SiO₂ (AYO) multilayer structures using a high-k Y₂O₃ film as a charge-trapping layer were fabricated for nonvolatile memory applications. This work focused on improving the retention properties using a Y₂O₃ layer with different tunnel oxide thickness ranging from 3 nm to 5 nm created by metal organic chemical vapor deposition (MOCVD). The electrical properties and reliabilities of each specimen were evaluated. The results showed that the Y₂O₃ with 4 nm SiO₂ tunnel oxide layer had the largest memory window of 1.29 V. In addition, all specimens exhibited stable endurance characteristics (program/erasecycles up to 104) due to the superior charge-trapping characteristics of Y₂O3. We expect that these highk Y₂O₃ films can be candidates to replace Si₃ N₄ films as the charge-trapping layer in SONOS-type flash memory devices.

Simulated Programming Characteristics of Stacked-Gate Flash Memories with High-k Tunnel Dielectrics

Due to the reduced gate coupling ratio, the channel Fowler-Nordheim (CFN) programming speed of stacked-gate flash memories with high-permittivity (k) tunnel dielectrics (TDs) is helpless in operation voltage reduction. Although the electric field on high-k tunnel dielectrics is lower than SiO2 tunnel oxide, enhanced impact ionization rate and lower barrier height contribute to higher channel hot-electron (CHE) injection current and efficiency. Consequently, high-k TDs are only effective for the memories programmed with hot electron injection rather than FN tunneling, which is suitable for the NOR-type stacked-gate flash memories.

Core size dependence of the confinement energies, barrier heights, and hole lifetimes in Ge-core/Si-shell nanocrystals

The effect of the Ge core size on the confinement energies, barrier heights, and hole lifetimes in spherical Ge/Si core-shell nanocrystals is studied using an atomistic, tight-binding model with an sp3d5s* basis including spin-orbit coupling. Nanocrystal diameters range from 11 nm to 17.5 nm with Ge core diameters ranging from 1 nm to 7.5 nm. With a Ge core diameter of ~4 nm, and a Si shell thickness of ≥3 nm, the thermionic barrier presented by the Si shell increases the hole lifetime by a factor of ~2×108 compared to the hole lifetime in an all-Si nanocrystal in SiO2. A retention lifetime of 10 years is obtained with a 3 nm Ge core and a 3 nm Si shell with a 3 nm SiO2 tunnel oxide.

Improved charge storage characteristics of the tetralayer non-volatile memory structure using nickel nanocrystal trapping layer

Metal-oxide-semiconductor capacitors with a tetralayer structure consisting of nickel nanocrystals sandwiched between SiO2 and HfO2 tunnel and Al2O3 cap oxides were fabricated on p-Si substrates. Cross-sectional transmission electron micrographs revealed the formation of nickel nanocrystals having size 5–7 nm. The maximum charge injection capability (ΔVFB ∼ 7.8 V; @ ± 15 V) of nanocrystals was observed for the device RTA annealed at 950 °C for a minute. Charge storage and leakage current characteristics of the nanocrystal memory structures were studied through capacitance–voltage and current–voltage measurements, respectively. The improved retention properties with good thermal stability and endurance properties were also studied.

Tunnel Barrier Engineering for Non-Volatile Memory

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single SiO₂ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

Metallic nano-crystals for flash memories

To overcome the scaling limitation of standard polysilicon floating gate flash memory, Tiwari et al. have proposed the use of a granular semiconductor floating gate. Another improvement on this idea is to replace semiconductor nanocrystals (NCs) with metallic dots to allow more charge storage per dot and more flexibility over the barrier height with respect to the insulating dielectric.To evaluate this solution, we have studied the growth of nickel and platinum NCs on 4.5 nm SiO2 tunnel oxide using the thin film metal agglomeration (dewetting) phenomenon. The dot structure was investigated by SEM and XPS and it has been shown that the dot density and size can be controlled between 1E9–5E11 cm−2 and 10–60 nm using a conventional 200 mm processing tool. Nice isolated dots with sufficient densities (>1E11 cm−2) and surface coverage (∼30%) have been elaborated at temperatures around 450 °C. It has also been shown that lower annealing temperatures (280 °C) are insufficient to form isolated dot-like structures and that surface coverage decreases rapidly at high temperature (700–850 °C). In addition, annealing tests on Ni-NCs at high temperature (850 °C) have demonstrated that tunnelling barrier can be easily destroyed by metal diffusion and chemical reaction at SiO2/Si interface (silicide formation).To conclude, using only the annealing temperature and time, it has been possible to control dot density and size to a level which approaches that of Si-based NC memories currently being studied. However, NVM technologies based on metals must solve the problem of low thermal budget, otherwise, metal diffusion into tunnelling barriers will compromise devices performances.

Effect of SiO2 Tunnel Oxide Thickness on Electron Tunneling Mechanism in Si Nanocrystal Dots Floating-Gate Memories

The effect of tunnel oxide thickness on the charging/discharging mechanism and data retention of Si nanocrystal dot floating-gate devices was studied. The key point here is the difference in tunnel oxide thickness. Other parameters that can affect memory properties were carefully controlled. The mechanism of electron discharging was discussed on the basis of the difference in tunnel SiO2 thickness. Direct tunneling was found to dominate in the 3- and 5-nm-thick SiO2 tunnel oxides. However, Fowler–Nordheim (FN) tunneling affects the electron discharging characteristics of a thicker SiO2 tunnel oxide. It was found that memory properties also strongly depend on tunnel oxide thickness.

Effect of nitridation on Fowler–Nordheim tunneling coefficients in SiO2 MOS capacitors with WSi2-polysilicon gate

In this work we have studied the influence of N2O nitridation of thin EEPROM SiO2 tunnel oxides on Fowler–Nordheim tunnel injection potential barrier heights in WSi2-polysilicon gate MOS structures. In particular we have paid attention to the effect of the nitridation temperature by means of a comparison with standard (dry-wet-dry) oxides annealed in N2 at the same temperature. The temperatures considered were 900 °C, 950 °C and 1000 °C. It has been shown that the Si/SiO2 barrier is systematically smaller than the poly-Si/SiO2 one (~0.05 eV) in the whole set of samples and that the nitridation in N2O systematically decreases both the Si/SiO2 and the poly-Si/SiO2 barrier heights all the more as the nitridation temperature increases. The effects of neglecting the contribution of Si/SiO2 interface states and of the gate depletion phenomenon in the evaluation of the oxide electric field and, as a consequence, in the evaluation of the tunnel injection potential barrier heights have also been considered. It has been shown that neglecting the polysilicon gate depletion phenomenon leads to a strongly over-evaluated value of the Si/SiO2 barrier height while neglecting the interface states gives an error of approximately 1%. Moreover, we have shown that N2O nitridation increases the oxide dielectric constant all the more as the nitridation temperature increases while fluorine incorporation into the oxide induced by the WSi2 polycide deposition process decreases the same constant.