SiO2 Stack Research Articles

A Study on the Channel Holes’ Diameter Effects of High-Performance Vertical-Channel Flash Memory Cells

High-performance vertical-channel flash (HVF) memory cells were fabricated on the single crystalline Si (c-Si) sidewalls of the cylindrical deep wells in c-Si substrate. To investigate the diameter effects of the cylindrical deep wells, namely channel holes, on HVF cells, the channel holes with different diameters, ranging from 65 nm to 260 nm, were made. Memory gate stacks of SiO2/Al2O3/HfO2/Al2O3/TiN/W were formed by ozone oxidation and then ALD with the deposition thicknesses of 1/5/7/8/2/150 nm, respectively. For the devices with their diameters equal to or greater than 150 nm, their electrical properties, such as Vt, SS, DIBL, and program/erase characteristics, are close. As expected, DIBL and SS become better as the diameter increasing due to better gate control with larger diameter. However, large changes were occurred for the devices with the diameters of 90 nm and 65 nm. A simple model based on cylinder bulk for vertical flash memory devices was presented to obtain an approximate analytical solution for depletion-width and explain our experimental data. For the devices with the diameters of 150 nm, the high On/Off current ratio of 107 and relatively large memory window of 4.5 V were achieved. However, programming/erasing efficiency were degraded with hole diameter decreasing.

DM-PA-CNTFET Biosensor for Breast Cancer Detection: Analytical Model

In this paper, an analytical model for a novel design dielectric modulated plasma-assisted carbon nanotube field-effect transistor (DM-PA-CNTFET) biosensor is proposed for breast cancer detection. This work is based on a PA-CNTFET in which CNT is used as a channel of FET, and various other device engineering techniques such as dual metal gate-all-around structure and dielectric stack of SiO2 and HfO2 have been used. A comparative analysis of DS-GAAE-CNTFET was performed using a silicon gate all-around FET (Silicon-GAA-FET)-based biosensor. Early detection of breast cancer is made possible by immobilizing MDA-MB-231 and HS578t into the dual-sided nanocavity, which alters the electrical properties of the proposed CNTFET-based biosensor. The DS-GAAE-CNTFET sensor demonstrates a drain ON current sensitivity of 236.9 nA and a threshold voltage sensitivity of 285.58 mV for HS578t cancer cells. Malignant MDA-MB-231 breast cells exhibit a higher drain ON current sensitivity of 343.35 nA and a corresponding threshold voltage sensitivity of 293.23 mV. The exceptional sensitivity and structural resilience of the DS-GAAE-CNTFET biosensor establish it as a promising candidate for early breast cancer detection.

From Accelerated to Operating Conditions: How Trapped Charge Impacts on TDDB in SiO₂ and HfO₂ Stacks

From Accelerated to Operating Conditions: How Trapped Charge Impacts on TDDB in SiO₂ and HfO₂ Stacks

Low-frequency noise in InSnZnO thin film transistors with high-quality SiO2 gate oxide stacks

Low-frequency noise (LFN) in InSnZnO (ITZO) thin-film-transistors (TFT) with high-quality SiO2 gate oxide (GO) stacks is studied. This stack is fabricated by the plasma enhanced chemical vapor deposition (PECVD) and comprises two single layers. One layer is deposited by a SiH4 source (SiH4–SiO2), and the other uses a tetraethyl-orthosilicate precursor (TEOS-SiO2). The drain current noise power spectral densities follow the typical 1/f rule, and the main origin of LFN changes with the variation of drain current intensities. At low drain current intensities, LFN is affected by grain boundaries in the channel. As the drain current intensities increase, LFN originates from the carrier number fluctuations in devices with single TEOS-SiO2 GOs and from the carrier number with correlated mobility fluctuations in devices with SiO2 stacks GOs. At extremely high drain current intensities, the contact noise acts as a significant source of LFN in devices with SiO2 GO stacks. According to the carrier number with correlated mobility fluctuation (ΔN−Δμ) model, the devices with optimal stacks GOs exhibit a relatively low trap density near the ITZO/SiO2 interface. Additionally, these devices have a lower border trap density in GOs compared to those with single compositions. It demonstrates that high-quality SiO2 stacks reduce traps near the SiO2/ITZO interface, leading to enhanced devices performance. This work provides a precise and efficient method to evaluate the quality of GOs in metal oxide TFTs.

Analysis of trap distribution and NBTI degradation in Al2O3/SiO2 dielectric stack

In this work, p-substrate MOS capacitors with plasma-enhanced atomic-layer-deposited Al2O3/ thermally-grown SiO2 dielectric stack (with a target equivalent oxide thickness of 4.2 nm) are investigated by means of the conductance method in a temperature range from 25 °C to 150 °C. The trap state density and energy level distribution in the silicon bandgap are extracted over the bandgap. Furthermore, negative bias temperature instability is analyzed by two-point capacitance–voltage characterization to evaluate the electrical stability and dielectric reliability of the Al2O3/SiO2 stack. The contributions from interface and oxide trap generations are detailed. Our results indicate that plasma-enhanced atomic layer deposited Al2O3 on thermal SiO2 stack features low interface trap density, and comparable dielectric reliability to conventional SiO2, SiOxNy, and high-k dielectric stacks.

Spray-coated SiO2/PECVD SiN[formula omitted] stack for the passivation of n[formula omitted] emitter of p-type Si solar cell

Inefficient passivation of phosphorous diffused emitter is one of the limiting factors contributing to lower efficiency in advanced p-type silicon solar cells. Stack of SiO2 and SiNx with the former as an intermediate layer beneath SiNx provides better emitter passivation in comparison to SiNx film alone. Thermal oxide is reported to provide the best passivation, but it is not industrially viable. We demonstrate spray SiO2/SiNx as a viable alternative to thermal SiO2/SiNx stack. A few nanometer thin (∼6.1 nm) spray SiO2 film was first time demonstrated on micrometer sized textured pyramid with full coverage over an entire deposited area. The passivation of symmetrical (n+-p-n+) structure shows iVoc∼660 mV and passivation uniformity over the entire wafer area for both the stacks. Voc∼630 mV is achieved on cells with spray and thermal SiO2 as a passivating layer. Similar front passivation is further verified by overlapping IQE in the shorter wavelength range. Therefore, incorporating SiO2 film deposited via an industrially viable spray-coating process as a passivating layer at the front provides overall cell performance similar to the thermally grown SiO2.

Effect of multilayer anti-reflective coating on spectral emissivity of area blackbody

An area blackbody is used as a standard radiant source for calibrating equipment of non-contact infrared temperature measurement. Tailoring the spectral emissivity of area blackbody is important for improving the accuracy of a temperature measurement system. In this work, a new antireflective coating (ARC) has been proposed and the first association it with area blackbody has been made to improve the emission in the 3–14 μm wavelength range. We have compared the single, dual and triple-layer of different ARC materials with a different combination. In each category, we have optimized the SiO2, Al2O3 and Si3N4 thin films layer stack as ARC coating and then compared radiation property of area blackbody covered by ARC. Numerical simulations of the spectral emissivity of the combination reveals that double-layer ARC is taken as the most excellent stack structure, which can realize spectral emissivity exceeding 0.9 with least material in the wavelength range from 3 to 13 μm. Physical mechanisms responsible for the increasing emissivity are elucidated as due to producing the gradual variation of the refractive index and the selection of each layer material directly affects emission performance. Considering excellent radiation property of area blackbody combined with ARC, this study can help pave the way for designing ideal area blackbody.

Interfacial Properties of nMOSFETs With Different Al2O3 Capping Layer Thickness and TiN Gate Stacks

In this article, the interfacial properties of nMOSFETs with different thickness high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping layer on an 8-nm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and TiN gate stacks have been investigated using electrical measurement and low-frequency noise at room temperature. It is shown that the predominant 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise is governed by the number fluctuations mechanism. It is indicated that: 1) presence of an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping layer increases the noise power spectral density and, hence, the oxide trap density has an influence on the low-field mobility further and 2) effective work-function and the threshold voltage of nMOSFET should be modulated using the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping layers.

Non-volatile memory behavior of interfacial InOx layer in InAs nano-wire field-effect transistor for neuromorphic application

Nano-wire (NW) field-effect transistor (FET) is expected to be a promising device in the semiconductor industry owing to its scalability and enhanced gate-controllability. Particularly, III–V compound semiconductor-based NW FETs enable low power consumption because of their high mobility. In this study, a novel charge injection memory (CIM) device is presented using intrinsic InAs NW with high electron mobility. A simple combination of InAs native oxide and SiO2 stack accommodates charge trapping sites to store a bit information, resulting in a memory window of over 5 V. This charge-trapping behavior of the InAs NW FET is confirmed for more than 1000 s at room temperature. The disclosure of the charge-trapping effect in the InAs CIM provides a glimpse of the simplified non-volatile memory devices based on III–V NWs. Additionally, the synaptic behavior of InAs CIM is investigated for neuromorphic application. Utilizing the synaptic characteristics of the InAs CIM, an artificial neural network is implemented for simple handwritten digit recognition. This indicates that the InAs NW FETs can be used as the hardware for neuromorphic computational architectures.

Simultaneous recording and marking of brain microstructures

The vast majority of techniques to study the physiology of the nervous system involve inserting probes into the brain for stimulation, recording, or sampling. Research is increasingly uncovering the fine microstructure of the brain, each of its regions with dedicated functions. Accurate knowledge of the placement of probes interrogating these regions is critical. We have developed a customizable concentric marking electrode (CME) consisting of an iron core within a 125 μm-stainless steel (SS) sheath for co-localization of targeted regions in the brain. We used a dielectric layer stack of SiO2, Al2O3, SiO2 to electrically encapsulate the iron core and minimize exposure area to avoid significant increases in inflammatory response triggered by the probes. The CME can record multi-neuronal extracellular firing patterns. Appropriate electrical polarity of the iron and SS components controls the deposition of iron microdeposits on brain tissue. We show that in vivo labels by this method can be as small as 100 μm, visible via noninvasive magnetic resonance imaging (MRI) as well as post-mortem histology, and illustrate how deposit size can be tuned by varying stimulus parameters. We targeted the CA3 area of the hippocampus in adult rats and demonstrate that iron microdeposits are remarkably stable and persist up to 10 months post-deposition. Using a single probe for recording and marking avoids inaccuracies with re-insertion of separate probes and utilizes iron microdeposits as valuable fiducial markers in vivo and ex vivo.

Effect of multilayer selective radiative anti-reflective coating on crystalline silicon photovoltaics for operating temperature reduction

ABSTRACT Low heat transfer coefficient of ethylene-vinyl acetate hinders heat evacuation, and this causes a rise in temperature of the laminated solar module under AM1.5 spectrum. A new selective radiative antireflective coating (SR-ARC) has been proposed for the temperature reduction of the solar module and also effort has been made to improve the absorption in the 300–1100 nm wavelength range. We have compared the single, dual, triple and quad-layer of different transparent ARC materials with a different combination. In each category, we have optimised the SiO2, Al2O3, Si3N4 and TiO2 thin films layer stack as ARC coating and then compared the stacks for their SR-ARC properties. .

Implementation of Synaptic Device Using Various High-k Gate Dielectric Stacks.

We investigate the characteristics of short-term and long-term synaptic plasticity in a Si-based fieldeffect transistor (FET)-type memory device. An Al₂O₃/HfO₂/Si₃N₄/SiO₂ gate dielectric stack is used to realize short-term and long-term plasticity (STP/LTP). Si₃N₄ and HfO₂ layers are designed to charge trap layer for synaptic device. The mechanism of STP and LTP operation is analyzed by considering the device response to the potentiation and depression pulses and retention measurement of the memory functionality. To investigate the STP operation, paired pulse facilitation (PPF) measurement is performed. The retention characteristic is also studied to validate the LTP property of the device. By investigating a device with an Al₂O₃/HfO₂/Si₃N₄ stack as a control device, it is shown that the Al₂O₃/HfO₂/Si₃N₄/SiO₂ stack device is suitable for a synaptic device in neuromorphic systems.

Tuning the high-κ oxide (HfO2, ZrO2)/4H-SiC interface properties with a SiO2 interlayer for power device applications

SiC based power devices are promising for the next generation energy-efficient power converters. But its device performance is always largely limited by the tradition thermal SiO2 gate dielectric. The high-κ dielectric gate oxides have been widely used in Si and III-V devices. However, high quality dielectric layer using high-κ oxide for SiC power device is still lacking sufficient theoretical investigation. In this paper, the properties of XO2/4H-SiC (X = Hf or Zr) interfaces with a SiO2 interlayer are systematically studied by density-functional supercell calculations. Reliable interface atomic structures without any gap states have been built according to the electron counting rule. Based on the models, the electronic structure of each interface is obtained by hybrid functional. The interfacial characteristics including the averaged potential and charge transfer analysis are calculated in detail. The calculated band edge line-ups are comparable with the experimental reports. In term of the band alignment, HfO2 and ZrO2 directly bonding to SiC are not suitable dielectric materials for SiC based power device, due to the relatively smaller conduction band offsets (CBO). While introducing the SiO2 interlayer can effectively tune the interface properties, especially the band alignment. With HfO2(ZrO2)/SiO2 stack as the dielectric layer for 4H-SiC, the interface has the large CBO (>1 eV) to efficaciously confine the channel carriers, indicating that the HfO2(ZrO2)/SiO2/4H-SiC stack is the promising strategy for SiC based power device applications.

High performance metal-insulator-semiconductor-insulator-metal photodetector fabricated on a silicon-on-oxide substrate

We demonstrate a planar metal-insulator-semiconductor-insulator-metal (MISIM) photodetector fabricated on a silicon-on-insulator substrate where the insulator is a stack of SiO2 and HfO2. The detector exhibits an extremely low dark current, as well as a large sensitivity and responsivity for wavelengths in the 365–880 nm range. The current-voltage (I−V) characteristics under moderate illumination intensities are superlinear and saturate at high powers. This behavior is due to a space charge limited current mechanism, which causes a photocurrent amplification process. The current path through the detector is via filament sites induced by a voltage stress of the thermal SiO2 and HfO2 layers. These filaments allow for the internal photocurrent gain. Saturation of the I−V curves is caused by Schottky-type electrodes whose barrier height with silicon controls the thermionic emission of carriers through the filament sites to the silicon depletion region. At a bias of ±4 V, we estimated a maximum sensitivity of 1.25 × 105, a responsivity of 68 A/W, a detectivity of 6.5 × 1013 Jones, and a quantum efficiency of 2.3 × 104% of the photodetectors for an incident optical power of 0.143 μW at 365 nm wavelength.

Piezoelectric Pressure Sensors for Hypersonic Flow Measurements

A microelectromechanical-system piezoelectric pressure sensor targeting hypersonic flow applications is presented. The sensing diaphragms have 500- $\mu \text{m}$ diameter and are comprised of a composite stack of Si, SiO2, and AlN. This paper presents the fabrication and packaging details of the sensor and then presents test results from a Mach-6 hypersonic-flow facility, in which the prototype sensor data are compared against data from a mature commercial sensor present in the same tests. Salient hypersonic-flow features are observed in signals captured by the prototype. The package is comprised of an on-chip two-element array with 650- $\mu \text{m}$ pitch, and signals from the elements captured during hypersonic-flow tests are highly correlated. [2018-0196]

Highly sensitive photo-detectors for the ultra-violet wavelength range based on a dielectric stack and a silicon on insulator substrate

We propose and demonstrate planar metal-insulator-semiconductor-metal photodetectors fabricated on a silicon-on-insulator substrate with an n-type silicon device layer. The gate insulator comprises a double layer dielectric stack of SiO2 and HfO2. Detectors with different electrode geometries were characterized in a wide wavelength range: from 245 nm to 880 nm. A responsivity of 1.77 A/W was achieved at 405 nm independent of the illumination intensity, while at 245 nm, the responsivity was found to be nonlinear and at an intensity of 8 μW/cm2, it reached a record value of 30.5 A/W. Local fringing electric fields across asymmetric metal-insulator-semiconductor and metal-semiconductor junctions, stemming from the insulator stack and a reduction of the effective barrier height under illumination, are assumed to cause the high responsivity at wavelengths longer than 365 nm. The super linear rise in responsivity for wavelengths shorter than 285 nm is due to deep trap states which are charged by the injected electrons.

Reliability studies on biaxially tensile strained-Si channel p-MOSFETs

An integrated technology computer aided simulation framework is used for the first time to predict the reliability (degradation) of substrate-induced strained-Si channel heterojunction field effect transistors on relaxed Silicon-Germanium buffer layer with ultra-thin SiO2 and high-k gate stacks. State-of-the-art four-state nonradiative multiphonon model is used for the degradation studies. Single defects and trap studies have been taken up on devices subjected to negative voltage stressing at an elevated temperature. Threshold voltage shift (due to charge capture and emission processes) in virtually fabricated devices has been studied in detail. For the first time, non radiative multiphonon model is used to explain the degradation mechanisms (oxide defects dominating the partial recovery of threshold voltage after stressing) in strained-Si channel heterojunction field effect transistors. It is shown that degradation in strained-Si channel device on relaxed-SiGe buffer is more compared to its Si-channel counterpart.

Spectroscopic ellipsometry characterization of multilayer optical coatings

The performance of an optical coating stack depends on thickness and refractive index of each layer. In situ spectroscopic ellipsometry (SE) can track coating properties in real-time, but ex situ SE characterization is limited by the large number of unknown sample properties. We review various SE characterization strategies for multilayer structures using 37-layer alternating high-low index stacks of Ta2O5 and SiO2. A “tooling factor” for each coating material is developed to inform how the actual layer thicknesses compare to nominal specifications.We also introduce tests for sources of error that can occur during multilayer processing. Process drift may produce a gradual change in film properties, such as a slight increase or decrease in coating thickness or optical constants. This is modeled by adding a gradient to each tooling factor. User-error is also considered, where incorrect parameter entry produces an unintentional stack design. An erroneous layer is identified by systematically testing each layer. A “blind” test was performed to determine SE sensitivity to such errors, where a single layer was intentionally altered within a 37-layer stack, and systematic testing was able to resolve the altered layer thickness and position in the stack.

Plasma-enhanced chemical vapor-deposited SiN and liquid-phase-deposited SiO2 stack double-layer anti-reflection films for multi-crystalline solar cells

We successfully fabricated a double-layer anti-reflection film for multi-crystalline silicon solar cells through liquid-phase deposition to deposit silicon dioxide (SiO2) film on a multi-crystalline silicon surface and plasma-enhanced chemical vapor deposition to deposit silicon nitride (SiN) film on a SiO2 film surface. The SiO2 film thicknesses were 10, 15, and 20 nm, and the SiN film thickness was 60 nm. The reflectance of the substrate markedly decreased as the double-layer film was deposited. Moreover, with different film thicknesses, the minimal values of the reflectance were 4.91%, 2.75%, and 2.83% at the wavelengths of 609, 597, and 634 nm. The average reflection reached 6.92% when the thicknesses of SiO2 and SiN films were 20 and 60 nm in the wavelength range of 400–1100 nm. The minority carrier lifetimes of the multi-crystalline silicon substrates were 7.44, 7.21, and 7.27 μs at different film thicknesses. The short circuit current density and efficiency of the solar cell reached 34.52 mA/cm2 and 16.56% when the thicknesses of the SiO2 and SiN films were 20 and 60 nm, respectively. Low reflectance and good cell performance indicated that the double-layer film composed of SiO2 and SiN films were suitable for multi-crystalline silicon solar cells as the anti-reflection film.

Control of dipole properties in high-k and SiO2 stacks on Si substrates with tricolor superstructure

The concept of the tricolor superstructure (TCS), which is a triple-layer stack structure containing two types of high dielectric constant (high-k) layers (designated HK1 and HK2) and a SiO2 layer, is proposed to control the moment and the polarity of the interface dipole layer that are induced at the high-k/SiO2 interfaces. The interface dipole layer is formed by oxygen ion migration from the layer with higher oxygen areal density (σ) to that with lower σ. When the two high-k materials are selected with the order of σHK1 &amp;gt; σSiO2 &amp;gt; σHK2 in a SiO2/HK2/HK1/SiO2 TCS, the dipole directions of the interface dipole layers at the SiO2/HK2 and the HK1/SiO2 interfaces are aligned. Additionally, in the transposed SiO2/HK1/HK2/SiO2 TCS, the total polarity is reversed. The concept is demonstrated using Al2O3 and Y2O3 layers because they offer the order of σAl2O3 &amp;gt; σSiO2 &amp;gt; σY2O3. The two stacking sequence samples composed of SiO2/Y2O3/Al2O3/SiO2 and SiO2/Al2O3/Y2O3/SiO2 that were fabricated using superlattice technique by pulsed laser deposition obviously show opposite dipole polarities. Increasing repetition of the deposited TCS unit also causes the dipole moments to increase systematically. The TCS technique enables control of the properties of the interface dipole layer at high-k/SiO2 interfaces in amorphous systems.