SiO2 Interface Research Articles

Direct evidence of flat band voltage shift for TiN/LaO or ZrO/SiO2 stack structure via work function depth profiling

We demonstrated that a flat band voltage (VFB) shift could be controlled in TiN/(LaO or ZrO)/SiO2 stack structures. The VFB shift described in term of metal diffusion into the TiN film and silicate formation in the inserted (LaO or ZrO)/SiO2 interface layer. The metal doping and silicate formation confirmed by using transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS) line profiling, respectively. The direct work function measurement technique allowed us to make direct estimate of a variety of flat band voltages (VFB). As a function of composition ratio of La or Zr to Ti in the region of a TiN/(LaO or ZrO)/SiO2/Si stack, direct work function modulation driven by La and Zr doping was confirmed with the work functions obtained from the cutoff value of secondary electron emission by auger electron spectroscopy (AES). We also suggested an analytical method to determine the interface dipole via work function depth profiling.

Physical, chemical and electrical characterisation of the diffusion of copper in silicon dioxide and prevention via a CuAl alloy barrier layer system

Cu and CuAl alloy (90%:10% wt) films deposited on thermally grown SiO2 were studied using thermal stress testing in vacuum, N2 flow and atmosphere ambient all at a temperature of 500°C, in order to rigorously test the effectiveness of the incorporation of Al into a Cu film at preventing degradation of the metal layer and diffusion of Cu into the underlying SiO2 dielectric. Capacitance voltage testing of metal-oxide-semiconductor (MOS) devices, using the Cu and the CuAl alloy as the gate metal show the failure of the Cu reference set via diffusion of Cu at the metal / SiO2 interface in contrast to the stability of the CuAl alloy devices, even following a 500°C anneal in atmosphere ambient. The flatband voltage of the Cu reference MOS structures were altered by the application of an external applied voltage bias, consistent with the diffusion and mobility of Cu+ ions into the underlying SiO2 layer. Optical and scanning electron microscopies of the surface metal layers show the degradation and delamination of the pure Cu films throughout the experimental anneal stages, in contrast to the stability of the CuAl alloy. X-ray photoelectron spectroscopy shows the growth of Al oxide at the surface of the CuAl alloy following thermal anneal which acts to passivate the film, preventing Cu oxide formation which was identified in the pure Cu reference sample set. Transmission electron microscopy analysis shows the inter-diffusion of Cu at the Cu / SiO2 interface following anneal, in contrast to the CuAl alloy which shows the growth of a continuous barrier layer interface. Time-of-flight secondary ion mass spectroscopy (ToF-SIMS) was used to profile the entire metal / SiO2 / Si stack via 3 dimensional reconstructions, showing the inward diffusion of Cu within the Cu control samples and containment of Cu within the metal layer of the CuAl alloy samples.

Thermal conduction across a boron nitride and SiO2 interface

The need for efficient heat removal and superior thermal conduction in nano/micro devices has triggered tremendous studies in low-dimensional materials with high thermal conductivity. Hexagonal boron nitride (h-BN) is believed to be one of the candidates for thermal management and heat dissipation due to its novel physical properties, i.e. as a thermal conductor and electrical insulator. Here we report the interfacial thermal resistance between few-layer h-BN and its SiO2 substrate using the differential 3ω method. The measured interfacial thermal resistance is around ~1.6 × 10−8 m2K W−1 for monolayer h-BN and ~3.4 × 10−8 m2K W−1 for 12.8 nm-thick h-BN in metal/h-BN/SiO2 interfaces. Our results suggest that the voids and gaps between the substrate and thick h-BN flakes limit the interfacial thermal conduction. This work provides a deeper understanding of utilizing h-BN flakes as a lateral heat spreader in electronic and optoelectronic nano/micro devices with further miniaturization and integration.

Electric, dielectric and optical properties of Ga2O3 grown by metal organic chemical vapour deposition

Thin film (15-130 nm) of gallium oxide were grown by the industry relevant metal organic chemical vapour deposition (MOCVD) technique on p-type Si to check the possibility for integration of newly rediscovered wide bandgap material with the Si technology. Electric, dielectric and optical properties were studied and analyzed. To perform electrical characterization, Ga2O3 films were integrated into Al/Ga2O3/p-Si metal–oxide–semiconductor (MOS) capacitors. Relative dielectric permittivity, flat-band voltage shift and effective oxide charge density were obtained from C-V measurements. Spectroscopic ellipsometry measurements reveal that Ga2O3 deposited by MOCVD is a direct bandgap material with a large optical bandgap of about 5.1 eV. Both ellipsometrical and electrical results show formation of a thick interfacial SiO2.

Engineered Interfaces in Hybrid Ceramic–Polymer Electrolytes for Use in All-Solid-State Li Batteries

Composites of inorganic lithium ion conducting glass ceramics (LICGCs) and organic polymers may provide the best combination of properties for safe solid separators in lithium or lithium ion batteries to replace the currently used volatile liquid electrolytes. A key problem for their use is the high interfacial resistance that develops between the two, increasing the total cell impedance. Here we show that the application of a thin conformal SiO2 coating onto a LICGC followed by silanization with (CH3CH2O)3–Si–(OCH2CH2)–OCH3 in the presence of LiTFSI results in good adhesion between the SiO2 and the LICGC, a low resistance interface, and good wetting of Li0. Further, the cross-linked polymer formed on the surface of the silanated SiO2 interface formed from excess (CH3CH2O)3–Si–(OCH2CH2)–OCH3 prevents corrosion of the LICGC by Li0 metal. The use of SiO2 as a “glue” enables compatibilization of inorganic ceramics with other polymers and introduction of interfacial pendant anions.

Effect of SiO2 interlayer on the properties of Al2 O3 thin films grown by plasma enhanced atomic layer deposition on 4H-SiC substrates

Al2O3 films were grown by plasma enhanced-atomic layer deposition (PE-ALD) on 4H-SiC substrates, with and without the presence of a thin SiO2 layer. The collected data indicated the formation of amorphous, adherent, and uniform Al2O3 thin films with a thickness of about 30 nm. The electrical characterization has been performed on metal–oxide–semiconductor (MOS) structures by both capacitance–voltage (C–V) and current–voltage (I–V) measurements. All these analyses demonstrated a better dielectric behavior of the Al2O3 film deposited on the SiO2/SiC stack, with respect to that deposited directly on the SiC substrate. In particular, higher dielectric constant value, lower leakage current density, and higher breakdown field have been found in the Al2O3/SiO2/SiC stack. Hence, it has been argued that the presence of the interfacial SiO2 provides a better condition for the growth of high quality Al2O3 films. In this context, the film density has been evaluated, and strong difference has been found in the density values, The correlation between the better electrical properties of the Al2O3 films on SiO2 and their higher density has been demonstrated. These results provide useful insights on the possible application of these Al2O3 films as gate insulator in 4H-SiC metal-oxide-semiconductor field effect transistors.

Effect of ultrasonic treatment on the defect structure of the Si‐SiO2 system

AbstractThe effect of ultrasonic treatment (UST) on the defect structure of the Si‐SiO2 system by means of electron spin resonance (ESR), metallography, MOS capacitance technique and secondary ions mass‐spectroscopy (SIMS) is presented. The non‐monotonous dependence of the defect densities on the US wave intensity has been observed. The influence of the UST frequency on the ESR signal intensity of the defect centres depended on the defects type and structure and may becaused by vibrational energy dissipation which are a functions of defect's centers type. The influence of the UST on the Si‐SiO2 interface properties depends on the oxide thickness and crystallographic orientation. The density of point defects and absorbed impurities at the Si–SiO2 interface can be reduced and its electrical parameters improved by an appropriate choice of the UST and oxidation conditions. (© 2016 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

(Invited) First-Principles Study on Electron Conduction at 4H-SiC(0001)/SiO2 Interface

Silicon carbide (SiC) is attracted much attention due to its excellent physical properties, such as a high thermal conductivity, high breakdown strength, and large band gap. However, unlike Si metal-oxide-semiconductor (MOS) field-effect transistors (FETs), SiC-MOSFETs suffer from unacceptably low carrier mobility. Large amount of defects at SiC/SiO2 interface, which are generated in oxidation process, is expected to be one of the origins for the low carrier mobility. We carried out first-principles calculations based on density functional theory to reveal the relationship between the electronic structure and the interface defects appearing in the oxidation process. SiC has many different polytypes, determined based on their stacking along the [0001] direction. Stacking ordered ABCAB… is called hexagonal while that ordered ABABA… is called cubic. Among various polytypes, most widely used polytype for SiC-MOSFETs is 4H-SiC, in which Si and C atoms can occupy one of three positions along the [1-100] direction, normally labelled ABCBAB.... It was reported that interlayer states, whose charge density accumulates in the interlayer region, rather than near atomic sites, lie near the conduction band edge (CBE) in elemental semiconductors. Previous work looking at bulk SiC found that the interlayer states appear between subsequent SiC bilayers with cubic stacking, and lie at the CBE [1]. In the present study [2], we found by the electronic structure calculation for a 4H-SiC(0001)/SiO2 interface that the location of the interlayer states along the SiC CBE changes depending on the two possible interface models: the interface model where the top of the interface is the cubic face (cubic model) has interlayer states at the first bilayer of the interface, whereas one does not appear until the second bilayer for the interface model with the top of the interface being the hexagonal face (hexagonal model). When O atoms, which are expected to be introduced in the oxidation process, are sequentially inserted between Si and C atoms at the interface, the electronic structure of the valence band edge changes in the same manner whether the cubic or hexagonal face is the top layer of the interface. On the other hand, the insertion of O atoms removes the interlayer states of the CBE at the first SiC bilayer in the case of the cubic model, while there are no effects in the case of the hexagonal model. The interlayer states appear due to the difference in the electrostatic potentials between the Si-surrounded tetrahedral interstitial site and C-surrounded one. The inserted O atoms raise the electrostatic potential of the Si-surrounded site due to the strong electronegativity of O, removing the interlayer states from the interface of the cubic model. On the other hand, changes at the CBE are negligible in the case of hexagonal model since there are no states to remove at the first bilayer. The effect of the interlayer states at the CBE on scattering property was examined by electron-transport calculations [3]. Electrons at the CBE of the cubic model are significantly scattered by the defects because of the absence of the interlayer states while those at the hexagonal model is not. We also investigated the scattering property of the possible defects at the interface, e.g., C interstitial and carbonyl interstitial, and found that the scattering due to the absence of the interlayer states is larger than that of those interstitials. Since recent SiC-MOSFETs mainly use the conduction band as a channel, these results imply that the behavior of the interlayer states at the CBE might play an important role in the performance of SiC-MOSFETs. [1] Y. Matsushita, S. Furuya, and A. Oshiyama, Phys. Rev. Lett. 108, 246404 (2012). [2] C. Kirkham and T. Ono, J. Phys. Soc. Jpn. 85, 024701 (2016). [3] S. Iwase, C. Kirkham and T. Ono, in preparation.

Structure of Pr Oxide Films on Si Deposited by Reactive Sputtering

Down scaling of metal-oxide-semiconductor (MOS) devices has led to the drastic increase in leakage current through the gate oxides. This problem has forced us to replace the SiO2 gate dielectric by that with higher dielectric constant (high-k) 1,2). In the device application, the interface with Si plays a key role and in most cases is the dominant factor in determining the overall electrical properties1). For most actively investigated high-k materials typified by Hf oxide, however, the SiO2interfacial layer can be unavoidably formed due to the interface reaction, leading to the increase of the EOT. Praseodymium oxide forms an interfacial silicate layer which has a higher dielectric constant than that of SiO2 3,4). In this work, we will report the structure of Pr oxide films deposited by the sputtering method as well as their chemical states of the elements composing the film based on the analyses by cross-sectional transmission electron microscope (XTEM), X-ray diffraction (XRD) and X-ray photoemission spectroscopy (XPS). After organic removal cleaning, p-type Si (100) substrates were dipped in the diluted HF solution (4 %) for 2 min to remove the native oxide and leave the Si surface hydrogen-terminated. Praseodymium oxide thin films were deposited by reactive RF magnetron sputtering at room temperature in an ambient of Ar and O2 with the O2 flow rate fraction of 10 % at 1.5 Pa with the RF-power of 50 W using the 2” Pr metal target. The Si substrate was set at the off-centered position with respect to the sputtering cathode to avoid re-sputtering by the O- ions from the target surface5). Deposited film thickness evaluated by XTEM was typically 35 nm. Deposited films were post-annealed in an ambient of nitrogen (N2) for 30 minutes at temperatures of 300, 500 and 800 °C. In the XRD patterns obtained with the fixed grazing incident angle of 2 °, the dominant diffraction line of cubic PrO2 was observed in the course of the annealing up to 500 °C. After annealing at 800 °C, rearrangement of the crystalline structure occurred; the new diffraction line corresponding to hexagonal Pr2O3appeared. In fact, the phase transition was observed from cubic to hexagonal structure. In the XPS spectra observed at the interface between Pr oxides and Si substrates, the peak position of Pr3d5/2 consistently shifted to lower binding energies from 934.4 to 933 eV with increasing annealing temperature up to 800 °C. The Si2p spectrum was observed at lower binding energies than 103.9 eV corresponding to the SiO2. The O1s spectrum was found to be composed by two components at 530.3 eV of Pr2O3 and 531.7 eV of the Pr silicate6). The Pr silicate spectrum faintly observed in the as-deposited film became dominant with increasing annealing temperature. The XPS results revealed that the formation of the Pr silicate progressed as increasing annealing temperature. The XTEM image of deposited films revealed that the SiO2 layer was formed at the interface between the as-deposited film and the Si substrate, although the interfacial SiO2 layer was not detected in the in-depth profile by XPS analysis. The reason for this is probably the surface roughing during in-depth profiling by Ar sputter etching. After annealing at 800 °C, the film structure was completely changed from those after lower temperature annealing; the interfacial SiO2 layer was lost, and the Pr oxide film had three-layered structure composed by the amorphous silicate layer, the Pr2O3layer having poly-crystal islands located with equal spacing and the continuous columnar crystalline layer from the interface to the surface. References 1) G. D. Wilk, R. M. Wallace, J. M. Anthony, J. Appl. Phys. 89 5243 (2001). 2) A. I. Kingon, J. P. Maria, S. K. Streiffer, Nature (Lond.) 406 1032 (2000). 3) H. J. Osten, J. P. Liu, P. Gaworzewski, E. Bugiel, P. Zaumseil, Tech. Dig. Int. Electron Devices Meet. IEEE, Piscataway, NJ, 2000, p. 653. 4) A. Sakai, S. Sakashita, M. Sakashita, Y. Yasuda, S. Zaima, S. Miyazaki, Appl. Phys. Lett. 85 5322 (2004). 5) D. J. Kester, R. Messier, J. Vac. Sci. Technol. A 4, 496 (1986) 6) A. Fissel, J. Dabrowski, H. J. Osten, J. Appl. Phys. 91 8986 (2002).

Electrical Properties of Al2O3 Incorporated CeO2 Thin Films Deposited by RF Magnetron Sputtering

High-k materials have been widely investigated as a new gate stack in metal-oxide-semiconductor (MOS) devices1,2) because leakage current through the conventional SiO2 gate increases as scaling down of MOS devices. Among them, CeO2 is one of the most noteworthy materials3) because of its high dielectric constant of 26, chemical stability and the promising interfacial properties owing to the compatibility with Si in terms of the crystal structure and the lattice constant: the cubic fluoric structure, lattice mismatch as small as 0.35%. Cerium dioxide is, however, likely to crystalize even just after RF magnetron sputtering deposition at room temperature, leading to the increase of the leakage current along with grain boundaries4). In our preliminary study, we found that the thin films of Al2O3 doped CeO2 (Al2O3 as 10% composition) was kept amorphous after annealing up to 500 °C in a N2 atmosphere. In this work, we will report the electrical properties of the Al2O3 incorporated CeO2 to suppress the poly-crystallization of the films as a function of the wide Al2O3 composition range. The oxide composite of CeO2 and Al2O3 was prepared by the RF magnetron sputtering equipped with the combinatorial mask system5). The deposition was carried out using 2 targets of CeO2 and Al2O3 with the applied RF powers of 150 and 200 W, respectively, in an Ar atmosphere with an O2 introduction (10%) at room temperature at a pressure of 0.5 Pa. We prepared the combinatorial composition spread thin films, with the total thickness of 32 nm, in which Al2O3 composition ratio was changed in the range of 0 ~ 60% against CeO2 in a sample. In the deposition process, we repeated the following procedures 80 times; first, 0.16 nm thick CeO2 layer deposition: second, a wedge shaped CeO2 layer deposition with a thickness of 0 to 0.24 nm by the moving mask: finally, a wedge shaped Al2O3 layer with a thickness of 0 to 0.24 nm by the mask moving to the counter direction. After the deposition, we prepared 2 kinds of samples; one was annealed in a N2 atmosphere, the other in an O2 atmosphere at 500­­ °C for 30 minutes. Then, Pt dot electrodes were formed using the metal mask with the 100 µm in diameter openings on the surface of the annealed samples by sputtering. The electrical properties were characterized by I-V and C-V measurements. For the sample annealed in a N2 atmosphere, the leakage current density obtained from I-V characteristics at the electric field of -1 MV/cm decreased from around 1.0 × 10-6 to the minimum value of 1.0 × 10-8 A/cm2 with increasing Al2O3 composition from 0 to 20%. When the Al2O3 composition increased above 20% up to 60%, however, the leakage current density approached back to the value without Al2O3 doping. For the O2 annealed sample, the annealing effect was limited; the minimum leakage current density was around 1.0 × 10-7 A/cm2 at the Al2O3 composition of 10%. The leakage current density was greater than that without Al2O3 doping at the doping level excess 20%. From the result of C-V measurement at 1 MHz, the estimated dielectric constant of the films, assuming the interfacial SiO2 layer with a thickness of 3.5 nm, was rapidly decreased from 18 to 8 with the increase of the Al2O3 composition from 0 to 15%. For the higher Al2O3 composition than 15%, the estimated dielectric constant represented a constant value of 8. Judging from both view points of the leakage current and the dielectric constant, the optimum Al2O3 composition was considered to lie around 8%. Compared with the annealing in N2, the O2 annealing was not effective in improving electrical properties. REFERENCES 1) Wei Wang, Ning Gu, J. P. Sun and P. Mazumder, Solid-State Electronics 50, 1489-1494 (2006). 2) Dedong Han, Jinfeng Kang, Changhai Lin and Ruqi Han, Microelectronic Engineering 66, 643-647 (2003). 3) D. G. Lim, G. S. Kang, J. H. Yi, K. J. Ynag and J. H. Lee, Journal of the Korean Physical Society 51, 1085-1088 (2007). 4) H. Y. Lee, S. I. Kim, Y. P. Hong, Y. C. Lee, Y. H. Park and K. H. Ko, Surface and Coatings Technology 173, 224 (2003). 5) M. L. Green, K.-S. Chang, S. DeGendt, T. Schram and J. Hattrick-Simpers, Microelectronic Engineering 84, 2209–2212 (2007).

Effect of atomic layer deposition temperature on current conduction in Al2O3 films formed using H2O oxidant

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al2O3 films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al2O3 metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO2 capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al2O3 capacitors are found to outperform the SiO2 capacitors in the cases where the capacitors are negatively biased and the gate material is adequately selected to reduce virtual dipoles at the gate/Al2O3 interface. The Al2O3 electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al2O3 capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al2O3. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al2O3 capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al2O3/underlying SiO2 interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al2O3 films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450 °C ALD process is presently the most promising technology for growing high-reliability Al2O3 films.

(Invited) First-Principles Study on Electron Conduction at 4H-SiC(0001)/SiO2 Interface

The thermal oxidation process of a hydrogen-terminated 4H-SiC(0001) substrate is examined by performing the first-principles total-energy calculations based on the density functional theory. It is found that the oxidation process of a SiC(0001) substrate is different from that of a Si substrate, which proceeds in a layer-by-layer manner. CO2 molecules are mainly emitted from the SiC surface although CO2 emission becomes less favorable and CO molecules are emitted from the SiC/SiO2 interface. Except for the oxidation energy, the situation is the same with the case of a bare 4H-SiC(0001) surface. We conclude that the effect of the dangling bonds on the surface is marginal and the stress at the interface is responsible for the removal of C during the oxidation.

Studying tantalum-based high-κ dielectrics in terms of capacitance measurements

The trend of rapid development of microelectronics towards nano-miniaturization dictates the inevitable introduction of dielectrics with high permittivity (high-κ dielectrics), as alternative material for replacing SiO2. Therefore, studying these materials in terms of their characteristics, especially in terms of reliability, is of great importance for proper design and manufacture of devices. In this paper, alteration of capacitance in different frequency regimes is used, in order to determine the overall behavior of the material. Samples investigated here are MOS structures containing nanoscale tantalum based dielectrics. Layers of pure Ta2O5, but also Hf and Ti doped tantalum pentoxide, i.e. Ta2O5:Hf and Ta2O5:Ti are studied here. All samples are considered as ultrathin oxide layers with thicknesses less than 15 nm, obtained by radio frequent sputtering on p-type silicon substrate. Measuring capacitive characteristics enables determination of several specific parameters of the structures. The obtained results for capacitance in accumulation, the thickness and time evolution of the interfacial SiO2 layer, values of flatband and threshold voltage, density of oxide charges, interfacial and border states, and reliability properties favor the possibilities for more intensive use of studied materials in new nanoelectronic technologies.

Electrical Characteristics of SiO2 Deposited by Atomic Layer Deposition on 4H–SiC After Nitrous Oxide Anneal

Properties of SiO2 gate dielectric deposited by atomic layer deposition (ALD) on Si-face of 4H silicon carbide (SiC) were systematically studied. The interface state and effective fixed charge densities of ALD SiO2 on n-type 4H–SiC with various post deposition anneal (PDA) conditions were evaluated. It has been found that nitrous oxide (N2O) PDA not only reduces the effective fixed charge density, which includes the fixed oxide charge and charged interface states, at SiC/SiO2 interface but also decreases the gate leakage current. Negative effective fixed charge is observed at SiC/ALD SiO2 interface after N2O PDA. ALD SiO2-based lateral n-channel MOSFETs show high threshold voltage with the promising field-effect mobility and the peak field-effect mobility increases with N2O PDA temperature.

Surface effects in segmented silicon sensors

The voltage stability, charge-collection properties and dark current of segmented silicon sensors are influenced by the charge and potential distributions on the sensor surface, the charge distribution in the oxide and passivation layers, and by Si–SiO2 interface states. To better understand these phenomena, measurements on test structures and sensors before and after X-ray irradiation, and TCAD simulations including surface and interface effects are performed at the Hamburg Detector Lab. The main results of these investigations and ongoing studies are presented.

Trapped charge densities in Al2O3-based silicon surface passivation layers

In Al2O3-based passivation layers, the formation of fixed charges and trap sites can be strongly influenced by small modifications in the stack layout. Fixed and trapped charge densities are characterized with capacitance voltage profiling and trap spectroscopy by charge injection and sensing, respectively. Al2O3 layers are grown by atomic layer deposition with very thin (∼1 nm) SiO2 or HfO2 interlayers or interface layers. In SiO2/Al2O3 and HfO2/Al2O3 stacks, both fixed charges and trap sites are reduced by at least a factor of 5 compared with the value measured in pure Al2O3. In Al2O3/SiO2/Al2O3 or Al2O3/HfO2/Al2O3 stacks, very high total charge densities of up to 9 × 1012 cm−2 are achieved. These charge densities are described as functions of electrical stress voltage, time, and the Al2O3 layer thickness between silicon and the HfO2 or the SiO2 interlayer. Despite the strong variation of trap sites, all stacks reach very good effective carrier lifetimes of up to 8 and 20 ms on p- and n-type silicon substrates, respectively. Controlling the trap sites in Al2O3 layers opens the possibility to engineer the field-effect passivation in the solar cells.

Shielding of surface photogenerated charges by SiO2 coating for the photocatalytic degradation of air pollutants

TiO2 has promising applications in air purification and self-cleaning but is usually inactivated by floating particulate matters. The inactivation is due to the accumulation of photogenerated charges on TiO2 surface. The surface charges significantly enhance the adsorption of particulate matters and thus block incident light. To shield photogenerated charges on TiO2 surface, a series of nanocomposites composed of inner TiO2 nanocrystals and SiO2 coating was synthesized using ethylenediamine as SiO2 coating assistant. XRD, N2 adsorption/desorption, TEM, surface photovoltage, UV–vis, and GC-FID were used to study the effect of SiO2 coating on the structure of inner TiO2 nanocrystals, the ability of shielding surface charges, the adsorption of airborne particles, and the removal efficiency of toluene. The results showed that SiO2 coating efficiently shielded the photogenerated charges on the TiO2–SiO2 interface and reduced the adsorption of airborne particles but did not diminish the transfer of toluene from air to photocatalytic sites on the TiO2 surface. The crystallinity and crystal size of inner TiO2 gradually decreased with increased amount of SiO2 coating. TiO2@SiO2-50 with a small crystal size of 9.2nm and relatively high crystallinity showed the best photoactivity. This work may provide a new strategy to overcome the problem of TiO2 inactivation by haze pollution.

Analysis on Trapping Kinetics of Stress-Induced Trapped Holes in Gate Dielectric of Amorphous HfInZnO TFT

A comprehensive study was done regarding stability under simultaneous stress of light and negative gate dc bias in amorphous hafnium–indium–zinc-oxide ( $\alpha $ -HIZO) thin-film transistors. A negative threshold voltage ( $V_{\mathrm{ th}})$ shift and an anomalous hump were observed in transfer characteristics after the stress, and it is explained that these phenomena are caused by the hole trapping in the SiO2 gate insulator, not by interface state generation. Furthermore, capacitance–voltage ( $C_{G}$ – $V_{G})$ measurements were performed with various frequencies to investigate the vertical distribution of the trapped holes in the gate insulator. As a result, the correlation between the vertical location of the trapped holes and the influence on $C_{G}$ – $V_{G}$ characteristics were revealed clearly. First, at the beginning of the stress, photogenerated holes are mainly trapped at the $\alpha $ -HIZO/SiO2 interface and interfacial SiO2 in contact with the interface, which induces the negative $V_{\mathrm{ th}}$ shift. Second, as the stress time increases, the holes start to be trapped in the spatially deeper insulator, which leads to an additional hump in the $C_{G}$ – $V_{G}$ characteristics at sufficiently low frequencies.

Density-Functional Calculation of Carbon-Interstitial Energies in a 4H-SiC(0001)-SiO<sub>2</sub> Interface

An atomistic model for an abrupt 4H-SiC(0001)-SiO2 interface is constructed. By means of density-functional calculations within the local-density approximation, the energy landscape of a carbon interstitial in this structure is investigated and estimates for the diffusion barriers within bulk SiC and the energy difference between interstitial positions in the bulk semiconductor and the amorphous oxide are extracted both for the neutral defect and two charge states. The electronic structure of the neutral defect in its energetically most favorable position is analyzed by means of a hybrid exchange-functional calculation.

Correspondence: Reply to ‘On the nature of strong piezoelectricity in graphene on SiO2’

In our paper1 we provided an experimental evidence that the single-layer graphene (SLG) deposited on SiO2 grating substrate exhibits very strong out-of-plane piezoelectric effect, several times greater than that of the best piezoceramics such as lead-zirconate titanate. Simultaneously, the in-plane strain distribution was measured by micro-Raman scattering in an attempt to relate such unusual activity to the strain gradient expected in suspended graphene near the ridges. We appreciate the comment by Stampfer and Reichardt2 who noticed that our calculations of the in-plane strain based on ref. 3 were incorrect. The overestimation of the strain values, however, does not change the main conclusion of our paper, since the piezoresponse force microscopy measurements give the value of out-of-plane a.c. deformation, fully decoupled from the d.c. in-plane strain measured by micro-Raman. We recalculated the strain map and corrected the strain values that vary now in the range from −0.078 to +0.078%. Nevertheless, the strain ratio between supported and suspended graphene is still 2.5 (strain for suspended graphene is about +0.02%). Figure 1a,b displays both the corrected strain map and cross-section of the position of Raman line and recalculated strain. Below we reply in detail to other issues raised by Stampfer and Reichardt in their communication2. Figure 1 Strains in the single-layer graphene on the silicon grating. Gruneisen parameter suggested by Stampfer and Reichardt2 is related to graphene produced by mechanical exfoliation, whereas in our work1 we used graphene sheets prepared by CVD. These two materials differ by the number of intrinsic defects and, therefore, their behaviour under uniaxial or biaxial strain is different. This was exactly demonstrated in ref. 3, where the opposite sign of Gruneisen parameter for G-band was revealed for CVD graphene with respect to the exfoliated one. Therefore, we used the value reported in ref. 3 for our calculations which gave us a maximum strain of 0.078%. Stampfer and Reichardt2 questioned why we used the Gruneisen parameter for uniaxial strain. We believe that using the value for uniaxial strain is dictated by the nature of the substrate. Being periodical in one direction only, this feature naturally defines the symmetry of the graphene deformations as well. Therefore, we considered uniaxial strain in our work. Stampfer and Reichardt2 claim that our paper ‘…directly linked the observed piezoelectricity in graphene to the supposed high in-plane strain induced by the substrate…'. Indeed, the observed piezoresponse distribution (Fig. 3(b) of ref. 1) apparently correlates with the mechanical strain distribution in graphene. However, it does not mean that the observed piezoelectricity is associated with this strain (and its value!). Since no amplification of the piezoresponse is observed near the grating edges where the maximum strain gradient is expected, we only ruled out the in-plane symmetry breaking induced by discussed in-plane strain. Therefore, the conclusion of the paper remains the same, that is, chemical bonds generated between O and C atoms can indeed induce piezoelectric effect and, at the same time, affect the G-band position. Stampfer and Reichardt2 cast some doubt that the C–O bonds can form at the interface with graphene based on some data on carrier mobility. The formation of strong C–O bonds between graphene and SiO2 has been already proven both experimentally and theoretically (see, for example, refs 3, 4, 5, 6). This fact is strongly supported by the observed p-type conductivity in graphene via a charge transfer from the carbon in graphene layer to the oxygen-terminated surface of SiO2 (ref. 4). As such, the observation of a strong piezoelectricity due to formation of polar C–O bonds is not a surprise. Though some authors7 claim that only weak bonds are formed for the most stable geometry of C atoms, the very existence of the strong polarity of the graphene–SiO2 interface proves that it is not the case. All in all, we highly appreciate the comment by Stampfer and Reichard1 concerning the overestimation of the in-plane strain, however, it does not change the main conclusion of the paper, that is, the experimental observation of strong piezoelectricity in graphene/SiO2. We emphasize that, while an inhomogeneous interaction between graphene and underlying SiO2 substrate (caused for example, by the substrate morphology) can be responsible for the in-plane strain seen in Raman measurements, the observed piezoresponse is attributed to the formation of out-of-plane polar C–O bonds that may not be directly related to the in-plane deformation.