SiNx Insulator Research Articles

Improvement of electrical characteristics of InGaZnO thin film transistors by using HMDSO/O2 plasma deposited SiOCH buffer layer

In this work, we present the performance improved InGaZnO thin film transistors by inserting low temperature processed 10 nm thick SiOCH buffer layers between SiN x insulator and InGaZnO channel layer. The influences of oxygen flow rate during the deposition of SiOCH buffer layer have been intensively investigated. Basing on the analysis of hall effect measurement and Fourier transform infrared spectrum, the SiOCH buffer layer can effectively increase the carrier concentration of the channel layer by the hydrogen doping due to re-sputtering and diffusion effect. The InGaZnO thin film transistor with buffer layer exhibits an enhanced performance with mobility of 13.09 cm 2 /vs, threshold voltage of −0.55 V and I on /I off over 10 6 . In this work, we present the performance improved InGaZnO based thin film transistors by inserting low temperature processed 10 nm thick SiOCH buffer layers between SiN x insulator and InGaZnO channel layer. The influences of oxygen flow rate during the deposition of SiOCH buffer layer have been intensively investigated. Basing on the analysis of hall effect measurement and Fourier transform infrared spectrum, the SiOCH buffer layer can effectively increase the carrier concentration of the channel layer by the hydrogen doping due to re-sputtering and diffusion effect. • The SiOCH buffer layer was inserted between insulator and channel layer to modify the performance of InGaZnO TFT. • The influence of oxygen flow rate during the deposition of buffer layer on InGaZnO TFT has been investigated in detail. • The SiOCH buffer layer could increase the carrier concentration of adjacent InGaZnO layer by hydrogen doping effect.

Top-gated graphene field-effect transistors by low-temperature synthesized SiNx insulator on SiC substrates

Top-gated devices made from an epitaxial graphene film on a 4H-SiC substrate were fabricated. Atomic force microscopy and Raman spectroscopy results showed that a large-scale highly uniform monolayer graphene film was synthesized on the SiC substrate. A SiNx passivation film was deposited on a SiC graphene device as a top gate insulator by catalytic chemical-vapor deposition (Cat-CVD) below 65 °C. After the top gate electrode was formed on the SiNx film, no leakage current flowed between the gate and source electrodes. The transport characteristics showed clear ambipolar characteristics from 8 to 280 K, and the temperature dependences of the conductance and field-effect mobility of the devices implied that monolayer graphene devices can be successfully fabricated. Moreover, the position of the charge neutrality point after SiNx deposition was around 0 V, indicating p-doping characteristics. These results indicate that SiNx films synthesized by Cat-CVD can be used as gate insulators and that the carrier type may be controlled by adjusting the deposition conditions.

Effects of interface and bulk properties of gate-dielectric on the performance and stability of hydrogenated amorphous silicon thin-film transistors

In order to investigate the effects of interface and bulk properties of gate insulator on the threshold voltage (Vth) and the gate-bias induced instability of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs), four kinds of TFT structures were fabricated with SiNx and SiOx insulators stacked to make different combinations of the bulk and interface in the gate-dielectric layers. It was found that the Vth and the stability are independently controlled by tuning stoichiometry and thickness of the SiOx insertion layer between a-Si:H and SiNx. In TFTs with SiOx insertion layer of 50 nm thickness, on increasing oxygen/silicon (O/Si = x) ratio from 1.7 to 1.9, Vth increased from 0 V to 9 V. In these TFTs with a relatively thick SiOx insertion layer, positive Vth shift with negative bias stress was observed, confirmed to be due to defect creation in a-Si:H with the thermalization barrier energy of 0.83 eV. On reducing the thickness of the SiOx insertion layer down to approximately 1 nm, thin enough for hole injection through SiOx by tunneling effect, stable operation was obtained while keeping the high Vth value under negative stress bias. These results are consistently explained as follows: (1) the high value for Vth is caused by the dipole generated at the interface between a-Si:H and SiOx; and (2) two causes for Vth shift, charge injection to the gate insulator and defect creation in a-Si:H, are mutually related to each other through the “effective bias stress,” Vbseff = Vbs – ΔVfb (Vbs: applied bias stress and ΔVfb: flat band voltage shift due to the charge injection). It was experimentally confirmed that there should be an optimum thickness of SiOx insertion layer of approximately 1 nm with stable high Vth, where enhanced injection increases ΔVfb, reduces Vbseff to reduce defect creation, and totally minimizes Vth shift.

Improved interfacial and electrical properties of vanadyl-phthalocyanine metal-insulator-semiconductor devices with silicon nitride as gate insulator

We have investigated the interfacial and electrical properties of vanadyl-phthalocyanine (VOPc) metal-insulator-semiconductor devices by the measurement of capacitance and conductance. The devices have been fabricated on ordered para-sexiphenyl (p-6P) layer with silicon nitride (SiNx) as gate insulator. The VOPc/p-6P/SiNx devices have shown a negligible hysteresis, low series resistance, and high operated frequency. Bulk traps have been distinguished from interface traps by two loss peaks in conductance measurement. Trap densities and distribution of trap energy level have been obtained. The improved properties indicate that VOPc/ p-6P devices with SiNx insulator hold a great promise of application in flexible displays.

High reliability of vanadyl-phthalocyanine thin-film transistors using silicon nitride gate insulator

The reliability of vanadyl-phthalocyanine (VOPc) thin filmtransistors (TFTs) with silicon nitride (SiNx) gate insulator was investigated under bias stress conditions. The shift of threshold voltage in ambient air, in vacuum and at high temperature was discussed. The initial field-effect mobility and threshold voltage were 1.2 cm(2)/Vs and -4.22 V, respectively. After a gate bias stress of -20 V for 10,000 s in ambient air, the threshold voltage showed a small shift of less than 0.6 V. In vacuum at high temperature, the shifts of threshold voltage were also below 1 V and current change of devices under the same bias condition was negligible. The excellent reliability was attributed to the reduction of interface defect states between VOPc film and SiNx gate insulator. These results show that VOPc TFTs using SiNx insulator hold a great promise of application in active-matrix organic light emitting displays. (C) 2013 Elsevier B.V. All rights reserved.

Characterization of Low-Frequency Noise in Etched GaAs Nanowire Field-Effect Transistors Having SiNx Gate Insulator

Low-frequency noise in SiNx insulator–gate GaAs-based etched nanowire field-effect transistors (FETs) is investigated, focusing on the device size dependence and the effect of electron traps in the insulator. Intensity of the drain current noise is found to systematically increase when the nanowire width and gate length decrease, as indicated by the conventional FET noise model. Noise spectrum also changes continuously from 1/f to 1/f2 with the decrease of the device size, which is not observed in Schottky-gate nanowire FETs. Theoretical analysis shows that traps having short time constants mainly affect on the spectrum slope, whereas those having long time constants only shift the spectrum and do not affect on the slope. Observed size dependence of the spectrum slope is explained by broadening of the distribution of the time constant rather than the change in the combination of discrete traps having different time constants.

Characteristics of bottom gate a-Si TFT array for AM-OLEDs

The authors have fabricated bottom gate amorphous silicon thin film transistor (a-Si TFT) array using five-step lithography process. The device shows a field effect mobility of 0.43 cm2/(V·s), on/off ratio of 7.5×106 and threshold voltage of 0.87 V. The instability of a-Si TFT is ascribed to the defect state in the a-Si channel and SiNx/a-Si interface. The present a-Si TFT array with SiNx insulator could be a significant step towards the commercialization of active matrix organic lighting diode (AM-OLED) technology.

Threshold voltage control using SiNx in normally off AlGaN/GaN HFET with p‐GaN gate

AbstractThe threshold voltage (Vth) of normally off‐mode AlGaN/GaN junction heterostructure field‐effect transistors with a p‐type GaN gate can be successfully controlled by inserting a SiNx insulator between the p‐GaN and a Ni/Au electrode. The Vth can be controlled from +1 V to above +8 V. Moreover, the gate leakage current of transistors decreases and their gate voltage at which gate current steeply increases becomes higher. The mechanism of the threshold voltage change is analyzed by the equivalent circuit model. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

The impact of SiNx gate insulators on amorphous indium-gallium-zinc oxide thin film transistors under bias-temperature-illumination stress

The threshold voltage instability (Vth) in indium-gallium-zinc oxide thin film transistor was investigated with disparate SiNx gate insulators under bias-temperature-illumination stress. As SiNx film stress became more tensile, the negative shift in Vth decreased significantly from −14.34 to −6.37 V. The compressive films exhibit a nitrogen-rich phase, higher hydrogen contents, and higher N–H bonds than tensile films. This suggests that the higher N–H related traps may play a dominant role in the degradation of the devices, which may provide and/or generate charge trapping sites in interfaces and/or SiNx insulators. It is anticipated that the appropriate optimization of gate insulator properties will help to improve device reliability.

Electrical Properties of Metal–Insulator–Semiconductor Capacitors on Freestanding GaN Substrate

The electrical properties of GaN metal–insulator–semiconductor (MIS) capacitors with as-grown SiO2, annealed SiO2, and SiNx insulators were investigated by capacitance–voltage (C–V), current–voltage (I–V), and time-dependent dielectric breakdown (TDDB) measurements. The MIS capacitor with the SiNx insulator was determined to have a lower interface trap density of 1×1011 cm-2 eV-1 than the MIS capacitors with the as-grown and annealed SiO2 insulators. In addition, the dielectric lifetime of the SiNx insulator was extrapolated to be more than 20 years at an even high voltage at room temperature. These results indicate that the high insulator/GaN interface quality and high reliability required for high-performance power devices can be achieved by the deposition of the SiNx insulator on GaN.

Effect of a SiNx insulator on device properties of pentacene-TFTs with a low-cost copper source/drain electrode

We fabricated different SiNx insulators at a 150–350 °C deposition temperature by plasma-enhanced chemical vapor deposition (PECVD) and investigated the effect of SiNx insulator on the device properties of pentacene-TFTs with a low-cost copper source/drain electrode. A pentacene-TFT with a SiNx insulator at a deposition temperature of 300 °C exhibited the highest saturation mobility of 0.29 cm2 (V s)−1, the lowest threshold voltage of −8.9 V and an on/off current ratio of 5.3 × 106. The best performance of the device with a SiNx insulator at a 300 °C deposition temperature can be attributed to the electrical properties and a relatively large water contact angle of insulator, smooth insulator surface and better crystallinity of the pentacene active layer. The present organic thin-film transistors (OTFTs) with the PECVD SiNx insulator and the low-cost Cu electrode could be a significant step toward the commercialization of OTFT technology.

NOR-Type Nonvolatile Ferroelectric-Gate Memory Cell Using Composite Oxide Technology

We fabricated a NOR-type memory cell composed of a ferroelectric-gate thin-film transistor (FeTFT) and an insulated gate thin-film transistor (TFT), which were a memory element and a select switch, respectively. The FeTFT consisted of a heteroepitaxially stacked oxide structure of ZnO (n-type semiconductor)/Pb(Zr,Ti)O3 (PZT; ferroelectric)/SrRuO3 (bottom-gate electrode) on a SrTiO3 substrate. An insulated gate stack of Au/Ti (top-gate electrode)/SiNx (insulator) was formed on the ZnO film. The drain electrode of the FeTFT was common to the source electrode of the TFT. The current–voltage (Ids–Vgs) characteristics of the FeTFT exhibited a high ON/OFF ratio of 105 by applying sweeping bottom-gate voltages (Vgs) from -10 to 10 V. After the removal of gate bias, the ON and OFF states were preserved by the remnant polarization of the ferroelectric film. Moreover, the current–voltage characteristics of the TFT exhibited an ON/OFF ratio of 105. The field effect mobility of the TFT was estimated to be 25 cm2 V-1 s-1, which corresponded to an electron mobility of 26 cm2 V-1 s-1 measured for the ZnO film by a van der Pauw method. However, the field effect mobility of the FeTFT, typically 0.1 cm2 V-1 s-1, was quite different from those values. The difference in field effect mobility was attributed to whether current flowed along the ZnO/PZT or SiNx/ZnO interface. We also confirmed the write and read operations of the memory cell using pulse sequences.

Potential of Hot Wire CVD for Active Matrix TFT Manufacturing

AbstractHot Wire Chemical Vapor Deposition (HWCVD) is a fast deposition technique with high potential for homogeneous deposition of thin films on large area panels or on continuously moving substrates in an in-line manufacturing system. As there are no high-frequency electromagnetic fields, scaling up is not hampered by finite wavelength effects or the requirement to avoid inhomogeneous electrical fields. Since 1996 we have been investigating the application of the HWCVD process for thin film transistor manufacturing. It already appeared then that these Thin Film Transistors (TFTs) were electronically far more stable than those with Plasma Enhanced (PE) CVD amorphous silicon. Recently, we demonstrated that very compact SiNx layers can be deposited at high deposition rates, up to 7 nm/s. The utilization of source gases in HWCVD of a-Si3N4 films deposited at 3 nm/s is 75 % and 7 % for SiH4 and NH3, respectively. Thin films of stoichiometric a-Si3N4 deposited at this rate have a high mass-density of 3.0 g/cm3. The dielectric properties have been evaluated further in order to establish their suitability for incorporation in TFTs. Now that all TFT layers, namely, the SiNx insulator, the a-Si:H or μc Si:H layers, and the n-type doped thin film silicon can easily be manufactured by HWCVD, the prospect of “all HWCVD” TFTs for active matrix production is within reach. We tested the 3 nm/s SiNx material combined with our protocrystalline Si:H layers deposited at 1 nm/s in ‘all HW’ TFTs. Results show that the TFTs are state of the art with a field-effect mobility of 0.4 cm2/Vs. In order to assess the feasibility of large area deposition we are investigating in-line HWCVD for displays and solar cells.

Electrostatic potential perturbation at the polycrystalline Si∕HfO2 interface

Comparison between potential barriers at the interfaces of polycrystalline Si with SiO2, SiO2∕HfO2, HfO2, and HfO2∕SiNx insulators indicates substantial perturbation of the image-force barrier shape at the Hf-containing interfaces. The internal photoemission of electrons suggests that Hf introduces charged centers with signs depending on the silicon doping type. In addition, at the interfaces of polycrystalline Si with HfO2 the barrier height is reduced by 0.2eV as compared to the (100)Si case by an interface dipole layer.

Organic-Inorganic Hybrid Encapsulation for P3HT Field-Effect Transistors

AbstractWe investigated the effect of encapsulation on poly(3-hexylthiophe) (P3HT) bottom-gate field-effect transistors (BG-FETs) with a high on/off current ratio achieved by thermal annealing in N2 atmosphere. The intensity of the oxygen-related absorption peak in the Fourier-transform infrared (FT-IR) spectra of the P3HT films showed a correlation to the on/off current ratio of the FETs. In order to eliminate this oxygen-doping effect, we evaluated three types of encapsulation film: polymer insulator, SiNx, and polymer-SiNx hybrid insulator. We found that the polymer-SiNx hybrid insulator film can suppress both damage caused by the formation of the encapsulation layer and the doping caused by exposure to air. To investigate the effect of encapsulation, we calculated the time dependence of the unintentional dopant density of the P3HT film.

Silicon nitride deposited by ECR–CVD at room temperature for LOCOS isolation technology

For LOCOS application, silicon nitride (SiN x ) insulators have been deposited by ECR–CVD at room temperature and with N 2 flows of 2.5, 5, 10 and 20 sccm on pad-SiO 2 /Si or on Si substrates. The obtained SiN x /Si structures were used to analyze the SiN x characteristics. FTIR analyses reveal the presence of SiN and NH bonds. The refractive indexes between 1.88 and 2.48 and the thickness between 120 and 139 nm were determined by ellipsometry. With these thickness values, the deposition rates of 9.6–10.1 nm/min and the BHF etch rates of 2–86 nm/min were determined. On the SiN x /pad-SiO 2 /Si structures, the LOCOS process was performed. Optical and SEM microscopy analyses were used to investigate the SiN x resistance to thermal oxidation, made at 1000 °C, and the bird’s beak in the obtained LOCOS structures, respectively. These analyses reveal that SiN x insulator performed with N 2 flows higher than 2.5 sccm presented high quality to LOCOS isolation technology.

Epitaxial Lateral Overgrowth of GaN on SiC and Sapphire Substrates

The epitaxial lateral overgrowth (ELO) process for GaN has been studied using SiC and sapphire substrates. Both MBE and MOVPE growth processes were employed in the study. The use of SiO2 versus SiNx insulator stripes was investigated using window/stripe widths ranging from 20 μm/4 μm to 3 μm/15 μm. GaN film depositions were completed at temperatures ranging from 800 °C to 1120 °C. Characterization experiments included RHEED, TEM, SEM and cathodolumenescence studies. The MBE growth experiments produced polycrystalline GaN over the insulator stripes even at deposition temperatures as high as 990 °C. In contrast, MOVPE growth produced single-crystal GaN stripes with no observable threading dislocations.

Plasma enhanced selective area microcrystalline silicon deposition on hydrogenated amorphous silicon: Surface modification for controlled nucleation

Selective deposition of μc-Si on hydrogenated amorphous silicon is demonstrated using time-modulated silane reactant flow in a low temperature plasma enhanced process. Alternating cycles of thin silicon layer deposition and atomic hydrogen exposure result in silicon layers on receptive surfaces, with no net deposition on nonreceptive areas of the substrate. Selective deposition could be useful to form self-aligned contacts in hydrogenated amorphous silicon (a-Si:H transistor applications. However, a problem commonly observed in low temperature selective deposition is that the selective process tends to etch amorphous silicon, harming the devices. We describe a technique involving Mo metallization that stabilizes the a-Si:H surface with respect to hydrogen plasma exposure and allows selective μc-Si deposition on a-Si:H in device structures, while avoiding deposition on the top SiNx insulator material. Surfaces and subsequent selective nucleation and growth were characterized using atomic force microscopy, x-ray photoelectron spectroscopy, and Auger electron spectroscopy, which revealed the presence of Mo incorporation in the a-Si:H surface remaining after complete removal of the metal layer. A direct comparison of selective deposition experiments on films prepared with and without Mo treatment demonstrate that the metallization stabilizes nucleation of microcrystalline silicon on amorphous silicon surfaces.

Epitaxial Lateral Overgrowth of GaN on SiC and Sapphire Substrates

AbstractThe epitaxial lateral overgrowth (ELO) process for GaN has been studied using SiC and sapphire substrates. Both MBE and MOVPE growth processes were employed in the study. The use of SiO2 versus SiNx insulator stripes was investigated using window/stripe widths ranging from 2 μm/4 μm to 3 μm/15 μm. GaN film depositions were completed at temperatures ranging from 800°C to 1120°C. Characterization experiments included RHEED, TEM, SEM and cathodolumenescence studies. The MBE growth experiments produced polycrystalline GaN over the insulator stripes even at deposition temperatures as high as 990°C. In contrast, MOVPE growth produced single-crystal GaN stripes with no observable threading dislocations.