Single Wafer Research Articles

Mask design, fabrication, and experimental ghost imaging applications for patterned X-ray illumination.

A set of non-configurable transversely-displaced masks has been designed and fabricated to generate high-quality X-ray illumination patterns for use in imaging techniques such as ghost imaging (GI), ghost projection, and speckle tracking. The designs include a range of random binary and orthogonal patterns, fabricated through a combination of photolithography and gold electroplating techniques. We experimentally demonstrated that a single wafer can be used as an illumination mask for GI, employing individual illumination patterns and also a mixture of patterns, using a laboratory X-ray source. The quality of the reconstructed X-ray ghost images has been characterized and evaluated through a range of metrics.

Indirect bonding of MgO wafers based on intercalation crystallisation of amorphous MgO film

Breakthroughs in high-temperature sensors require the achievement of a high bonding strength using a single wafer material to overcome thermal expansion mismatch. In this context, to improve the bonding strength of MgO (100)/MgO (100) wafers, an indirect bonding method based on inserting an amorphous MgO film at the interface is proposed herein. Notably, this method increased the bonding strength from 7 to 10.7 MPa without the introduction of other materials. Grazing incidence X-ray diffraction (GIXRD) and transmission electron microscopy (TEM) results showed that the films crystallised to MgO (100) under the thermocompression bonding parameters of vacuum, 1200 °C, and 4.3 MPa. In addition, the deposition temperature affected the bonding strength. Particularly, the film deposited at 200 °C exhibited the best improvement effect, while those deposited at other temperatures were suboptimal. This method avoids bonding failure caused by a sharp difference in thermal expansion between materials at high temperatures. Consequently, this method provides a key technology to improve the high-temperature resistance of MEMS devices using MgO wafer bonding.

Ultrathin Crystalline Silicon Nano and Micro Membranes with High Areal Density for Low-Cost Flexible Electronics.

Ultrathin crystalline silicon is widely used as an active material for high-performance, flexible, and stretchable electronics, from simple passive and active components to complex integrated circuits, due to its excellent electrical and mechanical properties. However, in contrast to conventional silicon wafer-based devices, ultrathin crystalline silicon-based electronics require an expensive and rather complicated fabrication process. Although silicon-on-insulator (SOI) wafers are commonly used to obtain a single layer of crystalline silicon, they are costly and difficult to process. Therefore, as an alternative to SOI wafers-based thin layers, here, a simple transfer method is proposed for printing ultrathin multiple crystalline silicon sheets with thicknesses between 300nm to 13µm and high areal density (>90%) from a single mother wafer. Theoretically, the silicon nano/micro membrane can be generated until the mother wafer is completely consumed. In addition, the electronic applications of silicon membranes are successfully demonstrated through the fabrication of a flexible solar cell and flexible NMOS transistor arrays.

Semi-Supervised Learning for Simultaneous Location Detection and Classification of Mixed-Type Defect Patterns in Wafer Bin Maps

Identifying the patterns of defective chips in wafer bin maps (WBMs) in semiconductor manufacturing processes is crucial because different defect patterns correspond to different root causes of process failures. Recently, mixed-type defect patterns (i.e., multiple defect patterns in a single wafer) have become increasingly common owing to the increased complexity of semiconductor manufacturing processes. Previous methods for classifying mixed-type defect patterns in WBMs focused on outputting only the class labels of the defect patterns and not their locations, although location information of the defect patterns is useful for tracking the root causes of failure and improving processes. Moreover, most previous methods used only labeled WBM data, although a larger quantity of unlabeled WBM data are more accessible because of the costly process of label annotation. Therefore, in this paper, we propose a semi-supervised learning method for classifying mixed-type defect patterns and detecting their locations simultaneously using both labeled and unlabeled WBM data. The proposed method extends a recent unsupervised object detection method called Attend-Infer-Repeat in a semi-supervised manner to perform object detection and classification simultaneously. The performance of the proposed method is verified using WBM datasets of different sizes. The results demonstrate the effectiveness of the proposed method for classification and location detection.

Simulations of Modified Shallow Water Equation and Reaction Kinetics of Poly Etching on Single Wafer Process

With the downscaling of semiconductor feature size, single wafer wet etching has shown better within-wafer and wafer-to-wafer uniformity. According to previous research and analysis, liquid film thickness has a close relationship with etch loss, and numerical simulations have been applied to calculate liquid film thickness with fixed nozzle dispensing. This study investigated liquid film thickness with scanning nozzle processing and a modeled aqueous tetramethylammonium hydroxide (TMAH) poly etching method. A modified shallow water equation was used to calculate the liquid film thickness under nozzle scanning conditions. Additionally, the liquid film thickness and liquid velocity were coupled with a chemical reaction kinetic model to calculate the TMAH poly etching reaction rate on the wafer surface. Scan dispensing etch loss was calculated by integrating the reaction rate. Both the experimental and simulation results showed that the scan speed can affect within-wafer etch loss profile and that a fast scan speed could increase etch loss in wafer donut area. The simulation model could be a predictive tool for improving within-wafer etching profile.

A realistic assessment of the prospect of silicon be replaced by other materials for IC applications

Silicon is the most common material used in semi-conductor. It can be used to make single crystal silicon wafer. Though it has the widest usage, silicon has high calorific value. Also, the performance loss is high compared to silicon carbide and the operating temperature is relatively low compared to gallium oxide. Luckily, there are several materials that could possibly replace silicon. The first one is 2D semiconductor. The prospective evaluation of 2D semiconductors is high. But now the biggest problem is the low-resistance connections with them. The second one is gallium nitride. It has high hardness, melting point and stability. This makes it a good material for high temperature, high frequency and high power devices. However, excellent property brings high cost. This disadvantage prevents gallium nitride to be widely used. The last one is graphene. It has strong electrical conductivity, ultra-high strength, excellent electrical properties, and strong electron interaction. It has a higher carrier mobility than silicon. While every coin has two sides, producing graphene on a large scale is difficult and expensive. Besides, graphene is highly reactive with oxygen and heat. What’s more, zero band gap nearly makes it impossible to become a semi-conductor material. Even though there are many methods of opening the bandgap, these methods still bring inevitable drawbacks. All in all, there are still many problems to be solved when new materials replace silicon in integrated circuit applications.

An Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging

With the emergence of 3D integration and wafer level packaging, the pillar bumping process has become a critical processing step. As the process has matured, significant efforts have been made for optimization in terms of both production and cost. This is especially true for photoresist stripping, since thick photoresists are needed to pattern high aspect ratios and must be removed in subsequent steps to expose underlying metal films. In this study, the removal of a thick negative tone photoresist with solder pillar plated wafers were investigated using a dimethyl sulfoxide blend with a quaternary ammonium hydroxide. Emphasis was placed on exploring the feasibility of an extended bath life beyond 7 days. Coupon level beaker tests were used to provide insight into the swelling and dissolution mechanisms with fresh and aged chemistry. Additionally, several chemistries were compared to examine the effect of the quaternary ammonium hydroxide. Based on these findings, chemical aging studies were performed on 300 mm wafers using a highly customizable single wafer processing tool that combined soaking and a high-pressure spray processing to potentially prolong the bath age even further. In addition to stripping efficiency at extended bath life, the compatibly with pillar structures and seed layers is investigated. Results from the study highlight potential methods to extend bath life while maintaining photoresist stripping efficiency.

Crystalline-face-dependent photoelectrochemical properties of single crystalline CuGaSe2 photocathodes for hydrogen evolution under sunlight radiation

Photoelectrochemical (PEC) water splitting by using a electrode based on a single crystalline compound provide a good opportunity for studying on fundamental aspects of net semiconductor bulk properties related to PEC performance. In this study, single crystalline CuGaSe2 wafers exposed (321), (312), and (112) facets were used as sources of photocathodes for investigating PEC properties for water reduction into hydrogen under sunlight radiation related to their surface properties. A CuGaSe2 single crystalline ingot grown by using the zone melting method was cut along with different directions to obtain wafers with different crystal orientations. The electrical and electron-energy properties of wafers after annealing in an Se atmosphere indicated the formation of a Cu-deficient component on their surfaces when the wafers oriented (321) and (312) directions were used, whereas formation of a component was not observed on the wafer oriented in the (112) direction. Since the Cu-deficient component acted as a hole blocking layer to suppress the recombination of photoexcited carries at the heterojunction, photocathodes based on wafers having (321) and (312) orientations showed enhanced PEC performance for water reduction compared to the PEC performance of a photocathode based on a wafer having the (112) orientation. Highly active photocathodes for water reduction based on polycrystalline thin films usually have preferential (112) orientation, whereas those of densely packed powder forms would not be probable for controlling crystalline orientations. Therefore, present results would be a guide to achieve further improvements of PEC water reduction using such conventional systems.

Monolithic integration of embedded III-V lasers on SOI

Silicon photonic integration has gained great success in many application fields owing to the excellent optical device properties and complementary metal-oxide semiconductor (CMOS) compatibility. Realizing monolithic integration of III-V lasers and silicon photonic components on single silicon wafer is recognized as a long-standing obstacle for ultra-dense photonic integration, which can provide considerable economical, energy-efficient and foundry-scalable on-chip light sources, that has not been reported yet. Here, we demonstrate embedded InAs/GaAs quantum dot (QD) lasers directly grown on trenched silicon-on-insulator (SOI) substrate, enabling monolithic integration with butt-coupled silicon waveguides. By utilizing the patterned grating structures inside pre-defined SOI trenches and unique epitaxial method via hybrid molecular beam epitaxy (MBE), high-performance embedded InAs QD lasers with monolithically out-coupled silicon waveguide are achieved on such template. By resolving the epitaxy and fabrication challenges in such monolithic integrated architecture, embedded III-V lasers on SOI with continuous-wave lasing up to 85 °C are obtained. The maximum output power of 6.8 mW can be measured from the end tip of the butt-coupled silicon waveguides, with estimated coupling efficiency of approximately -6.7 dB. The results presented here provide a scalable and low-cost epitaxial method for the realization of on-chip light sources directly coupling to the silicon photonic components for future high-density photonic integration.

High-throughput manufacturing of epitaxial membranes from a single wafer by 2D materials-based layer transfer process

Layer transfer techniques have been extensively explored for semiconductor device fabrication as a path to reduce costs and to form heterogeneously integrated devices. These techniques entail isolating epitaxial layers from an expensive donor wafer to form freestanding membranes. However, current layer transfer processes are still low-throughput and too expensive to be commercially suitable. Here we report a high-throughput layer transfer technique that can produce multiple compound semiconductor membranes from a single wafer. We directly grow two-dimensional (2D) materials on III-N and III-V substrates using epitaxy tools, which enables a scheme comprised of multiple alternating layers of 2D materials and epilayers that can be formed by a single growth run. Each epilayer in the multistack structure is then harvested by layer-by-layer mechanical exfoliation, producing multiple freestanding membranes from a single wafer without involving time-consuming processes such as sacrificial layer etching or wafer polishing. Moreover, atomic-precision exfoliation at the 2D interface allows for the recycling of the wafers for subsequent membrane production, with the potential for greatly reducing the manufacturing cost.

Level Set Simulation on Single Wafer Wet Processing Improvement

To improve the single wafer process for wafer edge yield performance, the liquid film thickness is the key indicator to be investigated. The traditional measurement of liquid film thickness is difficult to execute, due to wafer spinning. The numerical method becomes essential to simulate the process. This paper uses the multiple flow level set method to simulate single wafer spin process. An inlet hydraulic jump is approximated by a two-dimensional axisymmetric approach with a collar inlet. Various spin rotation speeds, variable flow rates, different liquid types and contact angles are simulated. The results indicate liquid film discontinuity at a certain radius and a lower shear rate at the wafer edge. After modifying the process recipe based on the level set simulation result, the wafer edge yield shows improvement. This level set simulation model provides useful information for single wafer wet process control. The level set simulation results can estimate the liquid distribution on the wafer surface before the real process and can avoid experiments on production wafers and hence lead to a lower cost.

Mechanical characterization of thin films via constant strain rate membrane deflection experiments

The mechanical behavior of freestanding metal thin films (gold, aluminum, and nickel-molybdenum-tungsten alloy) is characterized using micro-tensile testing and membrane deflection experiment (MDE). Micro-tensile and membrane samples are simultaneously fabricated on a single wafer to avoid microstructural differences. A constant strain rate MDE methodology is developed to directly compare each test method. Finite element analysis is performed to investigate potential sources of error in MDE. Specifically, the effects of in-plane and out-of-plane misalignment, tip blunting, sample dimension, and substrate deformation are studied, and physical insights gained from the analysis were applied to the experiments. By comparing with the micro-tensile tests, it is experimentally demonstrated that the stress-strain curve of freestanding metal thin films can be successfully measured via constant strain rate MDE. In particular, yield stress shows a good agreement with that obtained from micro-tensile tests, demonstrating the usefulness of applying the constant strain rate methodology in MDE testing. Furthermore, MDE enables residual stress measurements of the deposited films. Constant strain rate MDE developed in this study can serve as a useful technique for high-throughput measurement of in-plane mechanical properties of metal thin films.

Methods of dislocation structure characterization in AIIIBV semiconductor single crystals

The development pace of advanced electronics raises the demand for semiconductor single crystals and strengthens the requirements to their structural perfection. Dislocation density and distribution pattern are most important parameters of semiconductor single crystals which determine their performance as integrated circuit components. Therefore studies of the mechanisms of dislocation nucleation, slip and distribution are among the most important tasks which make researchers face the choice of suitable analytical methods. This work is an overview of advanced methods of studying and evaluating dislocation density in single crystals. Brief insight has been given on the main advantages and drawbacks of the methods overviewed and experimental data have been presented. The selective etching method (optical light microscopy) has become the most widely used one and in its conventional setup is quite efficient in the identification of scrap defects and in dislocation density evaluation by number of etch pits per vision area. Since the introduction of digital light microscopy and the related transfer from image analysis to pixel intensity matrices and measurement automation, it has become possible to implement quantitative characterization for the entire cross-section of single crystal wafers and analyze structural imperfection distribution pattern. X-ray diffraction is conventionally used for determination of crystallographic orientation but it also allows evaluating dislocation density by rocking curve broadening in double-crystal setup. Secondary electron scanning electron microscopy and atomic force microscopy allow differentiating etch patterns by origin and studying their geometry in detail. Transmission electron microscopy and induced current method allow obtaining micrographs of discrete dislocations but require labor-consuming preparation of experimental specimens. X-ray topography allows measuring bulky samples and also has high resolution but is hardly suitable for industry-wide application due to the high power consumption of measurements.Digital image processing broadens the applicability range of basic dislocation structure analytical methods in materials science and increases the authenticity of experimental results.

Highly efficient operation and uniform characteristics of curved mirror vertical-cavity surface-emitting lasers

This study obtained highly uniform and efficient GaN-based vertical-cavity surface-emitting lasers with curved mirrors from a single wafer. The average threshold current (I th) and the optical output power (P max) of 14 chips measured up to 7.0 mA were 0.64 mA and 4.5 mW, respectively. The standard deviations of I th and P max were 6.7% and 5.1%, respectively. Additionally, the best chip showed maximum values of wall plug efficiency and output power of 13.4% and 7.6 mW, respectively, at 5.2 mA and 12.8 mA operating currents.

First Configurational Study of the CryoAC Detector Silicon Chip of the Athena X-Ray Observatory

The 50 mK cryogenic focal plane anticoincidence detector of the Athena X-ray observatory (CryoAC) is a silicon-suspended absorber sensed by a network of 400 Ir/Au transition edge sensors (TES) and connected through silicon bridges to a surrounding silicon frame plated with gold. The device is shaped by deep reactive ion etching from a single silicon wafer of 500 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m. In operating test of prototypes of the demonstration model of the CryoAC, we have highlighted the importance of the phonon hot spot in the signal generation. A fast response to the cosmic particle of a large area of about 4 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a thin 0.5 mm silicon absorber covered by a TES array can be assured by matching the array configuration to the size and properties of the hot spot. In this article, we present the preparatory study of a proposal for measuring the phonon hot spot that is predicted by the particle-absorber interaction model.

Wafer-scale detachable monocrystalline germanium nanomembranes for the growth of III-V materials and substrate reuse.

Germanium (Ge) is increasingly used as a substrate for high-performance optoelectronics, photovoltaics, and electronic devices. These devices are usually grown on thick and rigid Ge substrates manufactured by classical wafering techniques. Nanomembranes (NMs) provide an alternative to this approach while offering wafer-scale lateral dimensions, weight reduction, waste limitation, and cost effectiveness. Herein, we introduce the Porous germanium Efficient Epitaxial LayEr Release (PEELER) process, which consists of the fabrication of wafer-scale detachable Ge NMs on porous Ge (PGe) and substrate reuse. We demonstrate the growth of Ge NMs with monocrystalline quality as revealed by high-resolution transmission electron microscopy (HRTEM) characterization. Together with the surface roughness below 1 nm, it makes the Ge NMs suitable for growth of III-V materials. Additionally, the embedded nanoengineered weak layer enables the detachment of the Ge NMs. Finally, we demonstrate the wet-etch-reconditioning process of the Ge substrate, allowing its reuse, to produce multiple free-standing NMs from a single parent wafer. The PEELER process significantly reduces the consumption of Ge in the fabrication process, paving the way for a new generation of low-cost flexible optoelectronic devices.

Wafer-scale synthesis of a morphologically controllable silicon ordered array as a platform and its SERS performance.

In this study, we fabricated four different structures using single crystal silicon wafers for surface-enhanced Raman spectroscopy (SERS) applications. For single crystal silicon, different crystal orientations exhibit different physical and chemical properties. In chemical etching, the etching speed of different crystal planes also exhibits significant differences. We first used reactive ion etching (RIE) to process the surface of the substrate, and subsequently used KOH anisotropic wet etching technology to modify the surface of silicon wafers with different crystal orientations and produced four different results. In the RIE stage in an O2 atmosphere, the (110) silicon wafer formed a hexagonal hole structure, and the (100) silicon wafer formed an inverted pyramid hole structure; however, in the RIE-treated substrates in O2 and SF6 atmosphere, the (110) silicon wafer formed a pyramid with a diamond-shaped base, and the (100) silicon wafer showed a columnar structure with a "straw hat" at the top. The formation mechanisms of these four structures were elucidated. We also performed structure-related SERS characterizations of the four different structures and compared their performance differences.

Composite Wafer Defect Recognition Framework Based on Multiview Dynamic Feature Enhancement With Class-Specific Classifier

Wafer defect pattern recognition is important for the manufacturing of semiconductor products. By recognizing the type of defect, the engineer can optimize the process of semiconductor manufacturing. Due to the complexity of the manufacturing process, composite defect types can occur on a single wafer map. As a result, there are even more than 30 defect types in real-life, which greatly increases the difficulty of recognizing. To address this problem, we propose a composite wafer defect recognition framework (CWDR-Net) based on a multi-view dynamic feature enhancement (MVDFE) module with a class-specific classifier. This framework can selectively extract information from the defect pattern, and class-specifically recognize each basic defect type. Specifically, the proposed MVDFE-Module can view the feature from 3 different perspectives and dynamically enhance it accordingly. In addition, the proposed framework applies a class-specific classifier that uses an attention mechanism to recalibrate the feature for each type of basic defect respectively. A real dataset with 8 basic single-type defects, and 29 mixed-type composite defects is used to evaluate this framework. The results show that the proposed framework can effectively recognize composite defects and outperform other state-of-the-art methods.

LOW-TEMPERATURE RADICAL ISSG OXIDATION OF SILICON, "Электронная техника. Серия 3. Микроэлектроника"

The kinetics of single wafer radical oxidation of a silicon during a low-temperature (500…800 °C) in situ steam-generation (ISSG) oxidation process based on hydrogen combustion is investigated. To determine the constants of radical oxidation, the obtained dependences of the oxide thickness on time at different temperatures and fixed other parameters of the technological process were used. It is shown that the rate of low-temperature radical ISSG oxidation corresponds to the exponential growth law. The self-limitation of the oxide thickness observed at temperatures below 700 °C is of great practical importance for the formation of a thin dielectric with a thickness of less than 1 nm, since it allows to control the process of oxidation by temperature, and not by processing time as with standard thermal oxidation.

Heteroepitaxially grown semiconductors on large-scale 2D nanomaterials for optoelectronics devices

Semiconductor nanostructures or thin films are vital components of modern optoelectronic devices, such as light-emitting diodes, sensors, or transistors. While single crystalline wafers are used as heteroepitaxial templates for them, increasing demands on flexibility or transferability require separation of the grown semiconductor structures on such substrates, which is technically challenging and expensive. Recent research suggests that large-scale 2D nanomaterials can serve as heteroepitaxial templates and provide additional functionalities such as transferability to foreign substrates or mechanical flexibility. In this paper, growth, structural properties, and optoelectronic device applications of semiconductor nanostructures or thin films which are heteroepitaxially grown on large-scale 2D nanomaterials are reviewed.