This special issue of Analog Integrated Circuits and Signal Processing presents the extended versions of selected papers from the 31th NORCHIP conference which was held in Vilnius, Lithuania, November 11–12, 2013. The 31th NORCHIP conference had 56 registered participants and 45 papers were presented during the 2 days the conference lasted whereof 30 papers were presented in 10 oral lecture sessions in two tracs, 12 papers were presented in two poster sessions, the 3 presentation, in session on Education and Training. The 3 invited presentations (first—Romualdas Navickas, ‘‘Self-formation in high speed integrated circuits’’, second—Petar Popovski, ‘‘Wireless technologies competing for a seat in the 5G bandwagon’’, and third—Ville Eerola, ‘‘Correlator design and implementation for GNSS receivers’’) were given. However, more submissions are originating from the local area of the conference (only one accepted paper was from a non-European country). From the contributed papers nine papers have been selected for this special issue. The selection of the papers for this special issue is based on quality criteria and they reflect the topics in analog circuit design highlighted during the conference, the feedback of the session chairs and the selected papers all contain contributions that will be of interest to the reader. The papers are briefly introduced below. The two first papers present two RF amplifiers. In the first paper ‘‘Triple Cascaded Current-Reuse Low Noise Amplifier’’ Muh-Dey Wei, Sheng-Fuh Chang, Renato Negra present a triple cascaded current-reuse CMOS low noise amplifier (LNA) for 3.5 GHz WiMAX application. Three commonsource amplifiers are stacked and reuse the same current. This triple cascaded topology is able to enhance power gain but needs two coupling networks which costs enormous chip size. In order to have reasonable chip size, two coupling methods are investigated. For obtaining simultaneous input and noise matching, an additional capacitor is employed to adjust quality factor and reduce the gate induced current noise. The proposed chip is implemented in 180 nm CMOS technology. The measurement results show a maximum power gain of 21.7 dB and minimum noise figure of 3.11 dB. The chip size is 1.05 9 0.93 mm including all pads and the power consumption is 5.16 mW with a supply voltage of 1.5 V. In the second paper ‘‘A 1 V Power Amplifier for 81–86 GHz E-band’’ authors Tobias Tired, Henrik Sjoland, Carl Bryant and Markus Tormanen describe the design and layout of a two stage SiGe E-band power amplifier using a stacked transformer for output power combination. In EMsimulations with ADS Momentum, at E-band frequencies, the power combiner consisting of two individual single turn transformers performs significantly better than a single 2:1 transformer with two turns on the secondary side. Imbalances in the stacked transformer structure are reduced with tuning capacitors for maximum gain and output power. At 84 GHz the simulated loss of the stacked transformer is as low as 1.35 dB, superseding the performance of an also presented alternative power combiner. The power combination allows for a low supply voltage of 1 V, which is beneficial since the supply can then be shared between the power amplifier and the transceiver, thereby eliminating the need of a separate voltage regulator. To improve the gain of the two-stage amplifier it employs a capacitive cross-coupling technique not yet seen in mm-wave SiGe Pas. Capacitive cross-coupling is an effective technique for gain enhancement but is also sensitive to process variations as shown by Monte Carlo simulations. To mitigate this two R. Navickas (&) Department of Computer Engineering, Vilnius Gediminas Technical University, Naugarduko str. 41, r. 437, 03227 Vinius, Lithuania e-mail: romualdas.navickas@vgtu.lt
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