Single-slope Analog-to-digital Converter Research Articles

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit.

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of -0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital).

In-ADC, Rank-Order Filter for Digital Pixel Sensors

This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems.

This paper presents a comprehensive timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope analog-to-digital converters (ADCs). The aim of the method is to optimize the read-out timing for each period in the image sensor's operation, while considering various factors such as ADC decision time, slew rate, and settling time. By adjusting the ramp reference offset and optimizing the amplifier bandwidth of the comparator, the proposed methodology minimizes the power consumption of the amplifier array, which is one of the most power-hungry circuits in the system, while maintaining a small color linearity error and ensuring optimal performance. To demonstrate the effectiveness of the proposed method, a power-efficient 108 MP 3-D stacked CMOS image sensor with a 10-bit column-parallel single-slope ADC array was implemented and verified. The image sensor achieved a random noise of 1.4 e-rms, a column fixed-pattern noise of 66 ppm at an analog gain of 16, and a remarkable figure-of-merit (FoM) of 0.71 e-·nJ. The sensor utilized a one-row read-out time of 6.9 µs, an amplifier bandwidth of 1.1 MHz, and a reference digital-to-analog converter (DAC) offset of 512 LSB. This timing optimization methodology enhances energy efficiency in high-resolution image sensors, enabling higher frame rates and improved system performance. It could be adapted for various imaging applications requiring optimized performance and reduced power consumption, making it a valuable tool for designers aiming to achieve optimal performance in power-sensitive applications.

A 1/f noise optimized correlated multiple sampling technique for complementary metal oxide semiconductor image sensor

SummaryCorrelated multiple sampling (CMS) technique is often used to reduce random noise in complementary metal oxide semiconductor (CMOS) image sensor, but as the number of samples increases, the suppression of 1/f noise by standard CMS based on averaging sampling gradually decreases. Therefore, in this paper, a 1/f noise optimized correlated multiple sampling (NOCMS) technique based on differentiated sampling weights is proposed. Transfer functions of standard CMS and NOCMS for analyzing the suppression effect of random noise respectively are derived based on the Fourier transform theory. And NOCMS shows a dramatic advantage in the suppression of 1/f noise. In addition, a circuit structure based on single‐slope analog‐to‐digital converter (SSADC) for implementing NOCMS is suggested. Ramp generator provides multiple sets of ramps with different slopes to quantify the reset and signal voltages of pixel output. Sampling weights are increased with the decrease of ramp slopes. The last reset and first signal values are weighted more due to their potentially higher correlations which highlights the principle of assigning weights. Simulation results under 110 nm CMOS technology illustrate that the input‐referred random noise is 142.9 V under standard CMS and 120.9 V under NOCMS when the number of samples equals 8. The noise reduction effect is improved by 15%. NOCMS makes it possible to further reduce 1/f noise of CMOS image sensor.

A Low-Power DROIC With Extended-Counting ADC for Uncooled Infrared Silicon Diode Detectors

A low-power digital readout integrated circuit (DROIC) for silicon diode uncooled infrared focal plane arrays (IRFPAs) is presented. The DROIC adopts a 14-bit column-level extended-counting analog-to-digital converter (ADC) based on a cascade of a coarse continuous-time Σ-ADC and a fine single-slope ADC. While the weak detector signal is integrated, the coarse conversion is implemented by a feedback current-steering digital-to-analog converter (IDAC), which shortens the signal chain and reduces the bandwidth requirement for the op-amp, to reduce power consumption. Besides, the ramp signal of the fine conversion is generated locally by an additional column-level IDAC, which matches the coarse conversion IDAC to decrease the DNL. Also, a low-power non-uniformity calibration circuit is adopted to compensate the non-uniformity of the IRFPA and adjust the ADCfs input signal range. The DROIC with 1024 ×768 pixel array is fabricated in a 0.18μm CMOS process. The experimental results demonstrate the DROIC consumes 109mW. The noise is 1.7LSB and the equivalent input noise voltage of the column circuit is about 2.1μVrms. The INL and DNL are less than +6.1LSB/.4.4LSB and +0.40LSB/.0.38LSB, respectively.

2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor

To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout technique is proposed, which optimizes the quantization method. And the proposed SS ADC prioritizes the quantization of the most significant bit (MSB), aiming to shorten the search range of the slope and greatly improve the quantization speed while ensuring accuracy. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed SS ADC is designed and simulated with 0.11-μm process. The simulation results show that the row time of SS ADC is 2 μs and the resolution is 500 ps, which greatly improves the quantization speed while ensuring power consumption and accuracy. The FoM is 182.6 fJ/step, which is a 7.1% improvement compared to other TDC-based SS ADCs. The proposed SS ADC becomes more effective as the bit-depth of the ADC increases.

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

CMOS Image Sensor With Two-Step Single-Slope ADCs and a Detachable Super Capacitive DAC

We present a CMOS image sensor (CIS) with a 10b two-step single-slope (SS) analog-to-digital converter (ADC) for achieving a high conversion rate with improved linearity. Because of the two-step conversion, the A/D conversion time is decreased by a factor of 16 relative to the conventional SS ADC. The column-parallel capacitive DACs (CDACs) are connected with a detachable super CDAC to enhance linearity. These CDACs generate the ramp signal required for coarse conversion. In addition, a fine correlated multiple sampling (CMS) scheme suppresses temporal noise without a significant time budget, and an input crossing comparison scheme suppresses column fixed pattern noise (CFPN) from the various input common-mode voltages. The prototype CIS was fabricated using a 110 nm CIS process and was fully characterized. The proposed two-step SS ADC achieves an integral nonlinearity of -0.89/+1.04 LSB and a differential nonlinearity of -0.67/+0.91 LSB. In addition, the prototype CIS has a temporal noise and CFPN of 0.243 mVrms and 0.14%, respectively.

Design and analysis on low-power and low-noise single slope ADC for digital pixel sensors

A Low-power and low-noise digital pixel sensor (DPS) is presented in this paper. To design and analyze the random noise (RN) of the developed DPS, especially, we utilize a novel simulationmethod called transient-based AC noise simulation (TBAS) which can effectively help to estimate the noise components of the lowpowered single-slope (SS) analog-to-digital converter (ADC). Based on this noise analysis, the high performance DPS has been successfully designed and demonstrated.

Comparison of Two in Pixel Source Follower Schemes for Deep Subelectron Noise CMOS Image Sensors

This paper compares two in-pixel source follower stage designs for low noise CMOS image sensors embedded both on a same 5 mm by 5 mm chip fabricated in a 180 nm CIS process. The presented chip embeds two pixel variants, one based on a body-effect-canceled thin oxide PMOS and the other embeds a native thick oxide NMOS. On the other hand they share the same sense node, same amplification circuit and 11 bit single slope analog to digital converter (SS-ADC). The imager characterization demonstrates a histogram peak noise of 0.34 e-RMS with the PMOS SF pixel and 0.47 e-RMS with the NMOS SF at maximum analog gain. This performance is obtained at room temperature and 119 frame per second. Both pixel variants demonstrate a full well capacity over 5600 electrons.

A 2.44μs row conversion time 12-bit high-speed differential single-slope ADC with TDC applied to CMOS image sensor

To improve the quantization speed of single-slope (SS) analog-to-digital converter (ADC), a cross-coupling input technique is proposed, which can automatically select the direction of input coupling according to the signal polarity. The proposed SS ADC is implemented and simulated through 110 nm process. The main clock frequency is 125 MHz. The simulation results show that the row conversion time of SS ADC is 2.44 μs, the resolution is 500 ps, and the power consumption is 129–198 μW. It is proved that these techniques can greatly improve the speed of quantization while ensuring power consumption and accuracy.

11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors

A first-step half-reference ramping (FHR) readout scheme is presented in this study for high frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the conversion speed of a single-slope (SS) analog-to-digital converter (ADC) by applying a binary-weighted searching algorithm at the first A/D conversion attempt. By effectively reducing the reference signal range, the proposed FHR readout scheme can reduce the number of A/D conversion steps in the SS ADC while maintaining the ADC performance. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed FHR scheme becomes more effective as the bit-depth of the ADC increases. A prototype CIS with a column-parallel 11-bit SS ADC was fabricated in a 0.11- $\mu \text{m}$ 1P4M CIS process with a 2.9- $\mu \text{m}$ pixel pitch. A maximum frame rate of 570 frames/s was achieved with a $1024\times240$ pixel resolution, corresponding to a 140.08 Mp/s pixel rate. Total power consumption was 57.2 mW under 2.8 V for pixel readout and 1.8 V for readout circuitry. When compared with the conventional 11-bit SS ADC, the proposed FHR scheme shortens the total A/D conversion time by 38.4%. The prototype CIS demonstrated the figure of merits (FoM) of 0.84 $\text{e}^{-}\cdot $ nJ and 0.41 $\text{e}^{-}\cdot $ nJ/step.

Low Bit-Depth ADCs for Multi-bit Quanta Image Sensors

A 1024 $\times $ 896 test chip is presented in this article to explore a low-power readout circuit for a multi-bit quanta image sensor (QIS). Five well-known analog-to-digital converter (ADC) approaches [flash, pipeline, successive approximation register (SAR), cyclic, and single-slope (SS)] are studied, and two types of ADCs, namely, SAR ADCs and SS ADCs, are implemented in the sensor. The ADC power dissipations are compared under the condition of constant imaging throughput in counting photoelectrons. In QIS devices, one LSB corresponds to one photoelectron. Measurement results show that the power consumption of SAR ADC is better than that of the SS ADC and decreases by a factor of 17 when the resolution is changed from 1 b to 6 bits. By contrast, the power consumption of the SS ADCs decreases by a factor of 2.5. Thus, SAR ADCs seem more suitable for use in low-power multi-bit QIS.

A Capacitive Pressure Sensor Interface IC with Wireless Power and Data Transfer.

This paper presents a capacitive pressure sensor interface circuit design in 180 nm XH018 CMOS technology for an implantable capacitive pressure sensor, which has a wireless power supply and wireless data transfer function. It integrates full-bridge rectifiers, shorting control switches, low-dropout regulators, bandgap references, analog front end, single slope analog to digital converter (ADC), I2C, and an RC oscillator. The low-dropout regulators regulate the wireless power supply coming from the rectifier and provide a stable and accurate 1.8 V DC voltage to other blocks. The capacitance of the pressure sensor is sampled to a discrete voltage by the analog front end. The single slope ADC converts the discrete voltage into 11 bits of digital data, which is then converted into 1 kbps serial data out by the I2C block. The “1” of serial data is modulated to a 500 kHz digital signal that is used to control the shorting switch for wireless data transfer via inductive back scatter. This capacitive pressure sensor interface IC has a resolution of 0.98 mmHg (1.4 fF), average total power consumption of 7.8 mW, and ±3.2% accuracy at the worst case under a −20 to 80 °C temperature range, which improves to ±0.86% when operated between 20 and 60 °C.

A Single Slope ADC With Row-Wise Noise Reduction Technique for CMOS Image Sensor

This paper presents a novel technique for single slope analog to digital converter (SSADC) to suppress the rowwise noise in CMOS image sensor. A sample switch is used in the current-steering DAC to reduce the noise introduced by bias circuits, which will deteriorate the characteristic of uniformity in the row direction. The sample switch can fix the voltage which biases the current source in the current-steering DAC when generating a ramp to avoid the ramp fluctuation in the time domain. The digital correlated double sampling is used to reduce the non-uniformity in column-level ADCs. The CMOS image sensor prototype is fabricated in 110nm 1P3M process. The 10-bit SSADC achieves DNL of -0.20 / +0.15 LSB and INL of -1.35 / +0.91 LSB at a sampling frequency of 29.2 KHz. It is proved that the row-wise noise is reduced from 764μVrmsto 163μVrmsat a frame rate of 228 fps using the proposed sample switch structure. The prototype photos taken by the sensor show that the row-wise noise is reduced under the low-illumination circumstance effectively.

Ultra-Low Power CMOS Image Sensor With Two-Step Logical Shift Algorithm-Based Correlated Double Sampling Scheme

This article presents an ultra-low power counter structure for a column-parallel single-slope analog-to-digital converter (SS-ADC) in CMOS image sensors. The proposed counter employs a two-step logical shift algorithm-based correlated double sampling (CDS) scheme. The logical shift algorithm can reduce parasitic capacitances, driving frequency, and inner toggling nodes by using the minimum number of transistors and a single-direction counter structure. Moreover, the two-step counting and double data rate scheme in the LSB counter can halve the operating clock frequency, resulting in further decreased power consumption. A prototype sensor was fabricated using a 110 nm CMOS image sensor process. The measurement results show that the proposed SS-ADC with a two-step counter consumes 2.4 μW power per column and shows a differential nonlinearity of +0.38/-0.25 LSB and an integral nonlinearity of +0.75/-0.5 LSB. The total power consumption is 2.25 mW for 640 × 480 effective image resolution at 60 frame rates with 3.3 V/1.5 V supply voltage.

A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors

A low-power column-parallel gain-adaptive single-slope analog-to-digital converter (ADC) for CMOS image sensors is proposed. The gain-adaptive function is realized with the proposed switched-capacitor based gain control structure in which only minor changes from the traditional single-slope ADC are required. A switched-capacitor controlled dynamic bias comparator and a flip-reduced up/down double-data-rate (DDR) counter are proposed to reduce the power consumption of the column circuits. A 12-bit current steering digital-to-analog converter (DAC) with a two-dimensional gradient error tolerant switching scheme is adopted in the ramp generator to improve the linearity of the ADC. The proposed techniques were experimentally verified in a prototype chip fabricated in the TSMC 180 nm CMOS process. A single-column ADC consumes a total power of 63.2 μ W and occupies an area of 4.48 μ m × 310 μ m. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are −0.43/+0.46 least significant bit (LSB) and −0.84/+1.95 LSB. A 13-bit linear output is acquired in nonlinearity within 0.08% of the full scale after calibration.

Design of a readout circuit incorporating a 12-bit analog-to-digital converter for cooled infrared focal plane array

The infrared focal plane array (IRFPA) is gradually becoming more systematic. In order to enhance the signal processing capabilities, analog-to-digital converters (ADC) integrated into the readout integrated circuit (ROIC) is an important development trend. However, the cryogenic effects of MOSFET devices will affect the conversion accuracy of the ADC at 77 K. In this paper, the main parameters of MOSFET are extracted at 77 K in 0.18 μm CMOS process, and a cryogenic model is established. Based on this, a digital ROIC is designed, which integrates a 12-bit single-slope integral ADC in pixel unit. By applying continuous integral ramp generator and mixed-voltage comparator, a high-linearity and low-power consumption single-slope ADC is realized for the cooled readout circuit. The measured dynamic effective number of bits of the ADC at 77 K is 10.92 bits, the static no-missing code resolution reaches 11.99 bits, the maximum differential nonlinear |DNL| < 1LSB and maximum integral nonlinear |INL| < 1LSB. This paper realizes the design of a digital ROIC for IRFPA and improves the simulation accuracy at 77 K.

A ripple-based adaptive on-time controlled buck converter with slope balance technique

A ripple-based adaptive on-time controlled buck converter with slope balance technique is presented in this paper. The slope balance technique provides a fixed switching frequency. A 4-bit single-slope analog-to-digital converter (ADC) was used to fix switching frequency when power supply was from 3.3 to 4.5 V. The slope balance technique is proposed to achieve an adaptive on-time control and without extra clock-controlled circuits and current sensing circuits. The input voltage can be predicted from the adaptive on-time by using 4-bit single-slope ADC control. Measurement results show that switching frequency is 1.448 and 1.438 MHz when load current is 200 and 1000 mA, respectively. The proposed buck converter was fabricated in 0.35 μm CMOS technology with a supply voltage of 4.5 V. The output voltage was measured to be 1.2 V and the load current range was determined to range 200–1000 mA.

High-DR CMOS Fluorescence Biosensor With Extended Counting ADC and Noise Cancellation

Accurately resolving small fluorescence power variations in presence of noise and high-background tissue autofluorescence from deep brain structures with a fiber photometry system requires highly linear and sensitive photo detectors. This paper presents a high-dynamic range (DR) CMOS biosensor fusing a low-noise photosensing front-end with a high-precision extended counting analog-to-digital converter (ADC) with noise cancellation to detect florescence neural signal fluctuations of very low incident power. The 7 MSBs are resolved by a first order continuous-time resettable $\Sigma \Delta $ ADC, whereas the residue voltage is quantized by a 10-bit single slope ADC for enabling wide-dynamic range and high-precision fluorescence sensing. The reset noise is canceled out by an embedded noise cancellation scheme which is subtracting the reset noise from the signal using a correlated double sampling scheme. Unlike other solutions, the biosensor has a short conversion time of $306.5~\mu \text{s}$ compared to a typical fluoresence sampling period of 10 ms, providing a very low duty cyle of 3%, which is a key to achieve low excitation source power consumption in this application to extend system autonomy, and to avoid photobleaching and phototoxicity in the tissue. The proposed optoelectronic biosensor is implemented in a 0.18- $\mu \text{m}$ CMOS technology, consuming $93~\mu \text{W}$ from a 3.3-V supply voltage while achieving a DR of 104 dB, a minimum detectable current of $1.3~\text {pA}_{\mathrm{ rms}}$ , and a chip area of 0.475 mm2. We present the measured performance of the biosensor using an optical experimental setup including a LED driver, a fiber optic, and a test board.