CMOS Image Sensor With Two-Step Single-Slope ADCs and a Detachable Super Capacitive DAC

Abstract

We present a CMOS image sensor (CIS) with a 10b two-step single-slope (SS) analog-to-digital converter (ADC) for achieving a high conversion rate with improved linearity. Because of the two-step conversion, the A/D conversion time is decreased by a factor of 16 relative to the conventional SS ADC. The column-parallel capacitive DACs (CDACs) are connected with a detachable super CDAC to enhance linearity. These CDACs generate the ramp signal required for coarse conversion. In addition, a fine correlated multiple sampling (CMS) scheme suppresses temporal noise without a significant time budget, and an input crossing comparison scheme suppresses column fixed pattern noise (CFPN) from the various input common-mode voltages. The prototype CIS was fabricated using a 110 nm CIS process and was fully characterized. The proposed two-step SS ADC achieves an integral nonlinearity of -0.89/+1.04 LSB and a differential nonlinearity of -0.67/+0.91 LSB. In addition, the prototype CIS has a temporal noise and CFPN of 0.243 mVrms and 0.14%, respectively.