Single Si Wafer Research Articles

Combinatorial Materials Design Approach to Investigate Adhesion Layer Chemistry for Optimal Interfacial Adhesion Strength

A combinatorial material adhesion study was used to optimize the composition of an adhesion promoting layer for a nanocrystalline diamond (NCD) coating on silicon. Three different adhesion promoting metals, namely W, Cr, and Ta, were selected to fabricate arrays of co-sputtered binary alloy films, with patches of seven different, distinct alloy compositions for each combination, and single element reference films on a single Si wafer (three wafers in total; W–Cr, Cr–Ta, Ta–W). Scratch testing was used to determine the critical failure load and practical work of adhesion for the NCD coatings as a function of adhesion layer chemistry. All tested samples eventually exhibit delamination of the NCD coating, with buckles radiating perpendicularly away from the scratch track. Application of any of the presented adhesion layers yields an increase of the critical failure load for delamination as compared to NCD on Si. While the influence of adhesion layers on the maximum buckle length is less pronounced, shorter buckles are obtained with pure W and Cr–Ta alloy layers. As a general rule, the addition of an adhesion layer showed a 75% improvement in the measured adhesion energies of the NCD films compared to the NCD coating without an adhesion layer, with specific alloys and compositions showing up to 125% increase in calculated practical work of adhesion.

A gatling-gun target delivery system for high-intensity laser irradiation experiments

Abstract Intense laser irradiation experiments of sub-micrometer scale targets are currently performed at slow shot rates. This limitation is the result of the inability to place such targets quickly and accurately in the focus of the laser. Here we present a target setup that enables irradiation at a high rate and sub-wavelength positioning accuracy. Three hundred targets were micro-machined and mounted on a single Si wafer. The system implements a closed feedback loop between a triangulation displacement sensor and a motorized manipulator. Using this setup, we demonstrate repeatable stable proton acceleration from 600 nm thick Au foils at a rate of 0.2 Hz. This system will enable studies that require a large overall dose, high statistical significance, or a fine scan of target geometric attributes.

Laser-driven semiconductor switch for generating nanosecond pulses from a megawatt gyrotron

A laser-driven semiconductor switch (LDSS) employing silicon (Si) and gallium arsenide (GaAs) wafers has been used to produce nanosecond-scale pulses from a 3 μs, 110 GHz gyrotron at the megawatt power level. Photoconductivity was induced in the wafers using a 532 nm laser, which produced 6 ns, 230 mJ pulses. Irradiation of a single Si wafer by the laser produced 110 GHz RF pulses with a 9 ns width and >70% reflectance. Under the same conditions, a single GaAs wafer yielded 24 ns 110 GHz RF pulses with >78% reflectance. For both semiconductor materials, a higher value of reflectance was observed with increasing 110 GHz beam intensity. Using two active wafers, pulses of variable length down to 3 ns duration were created. The switch was tested at incident 110 GHz RF power levels up to 600 kW. A 1-D model is presented that agrees well with the experimentally observed temporal pulse shapes obtained with a single Si wafer. The LDSS has many potential uses in high power millimeter-wave research, including testing of high-gradient accelerator structures.

Wafer-scale fabrication of target arrays for stable generation of proton beams by laser-plasma interaction.

Large-scale fabrication of targets for laser-driven acceleration of ion beams is a prerequisite to establish suitable applications, and to keep up with the challenge of increasing repetition rate of currently available high-power lasers. Here we present manufacturing and test results of large arrays of solid targets for TNSA laser-driven ion acceleration. By applying micro-electro-mechanical-system (MEMS) based methods allowing for parallel processing of thousands of targets on a single Si wafer, sub-micrometric, thin-layer metallic membranes were fabricated by combining photolithography, physical and chemical vapor deposition, selective etching, and Si micromachining. These structures were characterized by using optical and atomic force microscopy. Their performance for the production of laser-driven proton beams was tested on a purpose-made table-top Ti:Sapphire laser system running at 3 TW peak power with a contrast over ASE of 108. We have performed several test series achieving maximum proton energy values around 2 MeV.

(Invited) High Efficiency, Color-Tunable InGaN/GaN Nanowire Light Emitting Diode Arrays

The monolithic integration of red, green and blue (RGB) light-emitting diodes (LEDs) directly on a single chip is critically important for smart lighting and full-color display applications. The resulting color-tunable LEDs can exhibit excellent color rendering capability, high efficiency, and low power consumption, compared to conventional phosphor-based white LEDs. In this context, we have investigated the molecular beam epitaxial growth, fabrication and characterization of InGaN nanowire RGB LEDs monolithically integrated on a single chip, including Si and sapphire substrate. We have achieved controllable and tunable full-color light generation from InGaN LEDs. The correlated color temperature can be continuously varied in the range of 1900 K to 6800 K, while maintaining excellent color rendering index capability (CRI > 90). In this work, RGB InGaN/GaN dot-in-a-wire LED arrays were grown on Si using a three-step selective area growth (SAG) technique, wherein blue, green, and red-emitting LEDs were grown in sequence. In this process, a SiOx mask layer was used to protect the previously grown devices and also to precisely define the growth position of each nanowire LED pixel. Tunable PL emission across the entire visible spectral range (~450 nm to 700 nm) can be readily achieved on a single Si wafer by varying the sizes and/or compositions of the dots. By separately biasing such lateral-arranged multi-color LED subpixels, the CCT value can be varied from ~1900 K to 6800 K, while maintaining relatively high CRI values (up to ~ 90, or higher). We have further investigated the molecular epitaxial growth and fabrication of multi-color nanowire LED arrays on GaN template on sapphire substrate. In this process, a thin (~ 10 nm) Ti layer was utilized as the mask, and nanoscale growth patterns were defined by e-beam lithography. By controlling the nanowire diameters, multi-color emission can be achieved in a single epitaxial growth step. We have also demonstrated multi-color nanowire LEDs on sapphire substrate that can exhibit excellent current-voltage characteristics, high power operation, and reduced efficiency droop. In summary, we have developed tunable, full-color InGaN nanowire LED arrays on Si and sapphire substrate by using special selective area growth techniques. Through controlled light mixing at the wafer-level, we have demonstrated color-tunable light emission with an unprecedented tuning range for the CCT, from 1900 K to 6800K, while maintaining excellent CRI values. The realization of electrically injected RGB InGaN nanowire lasers is being studied and will also be reported.

Repeated epitaxial growth and transfer of arrays of patterned, vertically aligned, crystalline Si wires from a single Si(111) substrate

Multiple arrays of Si wires were sequentially grown and transferred into a flexible polymer film from a single Si(111) wafer. After growth from a patterned, oxide-coated substrate, the wires were embedded in a polymer and then mechanically separated from the substrate, preserving the array structure in the film. The wire stubs that remained were selectively etched from the Si(111) surface to regenerate the patterned substrate. Then the growth catalyst was electrodeposited into the holes in the patterned oxide. Cycling through this set of steps allowed regrowth and polymer film transfer of several wire arrays from a single Si wafer.

Hole mobility enhancement of p-MOSFETs using global and local Ge-channel technologies

Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on high hole mobility p-MOSFETs using global/local SiGe or Ge channels. There are two directions for introducing SiGe or Ge channels into Si CMOS platform. One is to use SiGe or Ge global substrates and the other is to form SiGe or Ge-channel regions locally on Si wafers. In both cases, the Ge condensation technique, where Ge-channel layers are formed by oxidizing SiGe films on SOI substrates, are effectively utilized. As for the global technologies, ultrathin GOI substrates are prepared and used to fabricate high mobility GOI p-MOSFETs. As for the local technologies, SGOI or GOI channels are formed locally in the active area of p-MOSFETs on SOI wafers. It is shown that the hole mobility enhancement factor of as high as 10 is obtained in locally fabricated p-MOSFETs through the effects of high-Ge content and the compressive strain. Furthermore, the local Ge-channel technologies are combined with global SiGe or Ge substrates for pursuing the optimal and individual design of n-MOSFETs and p-MOSFETs on a single Si wafer. The CMOS device composed of strained-Si n-MOSFETs and SGOI p-MOSFETs is successfully integrated on a same wafer, which is a promising CMOS structure under deep sub 100 nm technology nodes.

Anodizing Method Yielding Multiple Porous Seed Layers for the Epitaxial Growth of Monocrystalline Si Films

This paper reports on recent improvements in the fabrication of -thick self-standing porous Si seed films for monocrystalline epitaxy. A multiple three-step anodizing method allows us to separate multiple self-standing porous films from a single Si wafer with only one mounting step. So far, we have separated up to three self-standing porous films with diameters of (limited by our etch setup) with one continuous anodizing process. The porous films are used as seeding layers for monocrystalline Si epitaxy. Solar cells fabricated from -thick monocrystalline silicon films show independently confirmed efficiencies up to 13.6%.

Miniature fuel cells for portable power: Design considerations and challenges

We discuss key integration issues and engineering trade offs germane to all miniaturized fuel cell systems: thermal management, humidification control, water recirculation, air movement, fuel delivery, and power conditioning. We propose a design for a miniaturized protonexchange-membrane methanol-based fuel cell for powering 0.5–20 W portable telecommunication and computing devices. Our system is implemented on a silicon substrate to leverage advanced silicon processing and microelectromechanical systems technology enabling optimal fuel cell performance and minimizing production costs. We propose two alternative designs: a bipolar design using separate Si wafers for the anode and cathode and a monolithic design incorporating anode and cathode onto a single Si wafer.

Moisture sensitive field effect transistors using gate structure

A humidity sensing device, named a moisture sensitive field effect transistor (HUMIFET) has been fabricated on an n-type Si wafer using conventional VLSI technology. A series of sensors, each having area have been designed on a single Si wafer. The FET device is an n-channel MISFET with a duplex gate structure. A humidity sensitive layer of an anodically oxidized film of Al covers the under-gate electrode area and serves as a humidity sensitive film. The structure of the HUMIFET is and a thin porous gold (Au) layer on acts as the upper gate electrode. The device shows an enhancement mode characteristics with a threshold voltage of V at 33% relative humidity (RH) level which increases with decreasing RH level. The capacitance of the sensing film is measured and its temperature dependence is also observed. The drain current of the device is measured with RH at constant gate and drain voltages and the hysteresis area is found. The sensitivity of the device is 4.8 for the whole range of RH levels at constant gate and drain voltages. During a one month study on reproducibility, the device is found to be very stable. The response and recovery times of the device are and s respectively.

Realization of a delayed choice experiment using a multilayer cold neutron pulser

A delayed choice experiment was done using the cold neutron spin interferometer of Jamin-type arrangement which is installed at the JRR-3M of JAERI. A pair of identical composite neutron mirrors composes the pair of the wave splitters of the interferometer. The composite neutron mirror consists of a Ni/Ti multilayer ((Ni : 85 Å/Ti : 85 Å) × 5 (layers)), a Ge gap layer (4000 Å), and a Permalloy (Fe 55Ni 45)/Ge multilayer ((Permalloy : 85 Å/Ge : 85 Å)×5 (layers)) (PGM), evaporated in series on the single Si wafer in a magnetic field of 130 G. The second composite mirror was placed in the pulsed magnetic field for producing the conditions of whether the second wave splitter is introduced or not when a polarized neutron reaches the second wave splitter. It was shown that whether the interference fringe is obtained or not depends only on whether the second wave splitter is introduced or not, after the neutron passed through the first wave splitter. Delaying choice has no effect on the interference. We could deduce that the neutron propagates both ways with equal probability after being split by the wave splitter and does not choose one of two ways, as explained by quantum mechanics.

Flip chip bonding technique using transferred microsolder bumps

We have improved the microsolder bump technique previously used for fabricating a high-speed photoreceiver for high-speed and wideband coherent optical communication. To eliminate the damage caused by stress during vapor-phase deposition of the solder material and to enable the application of various high-speed electrical and/or photonic devices in conjunction with high-density interconnections, we have developed a flip-chip-bonding technique that uses microsolder bumps with a diameter of about 26 and 40 /spl mu/m. These bumps are transferred from a carrier substrate to a chip that is then bonded to the final substrate, This technique has three advantages. First, the stress during vapor-phase deposition does not damage the device because the bump formation process is separate from the device formation. Second, many applications are possible because we can make many carrier substrates with various chip sizes and bump pitches on a single Si wafer. Third, the chips with transferred microsolder bumps can be applied to devices that are known to be defect-free because the carrier substrates with the deposited solder bumps are individually aligned face-to-face with the base metal on the devices. We used solder materials of 100% In and 60% Sn-Pb in our experiments. From 8-546 transferred microsolder bumps were successfully formed on 0.5- to 4-mm-square chips (test samples and electrical and photonic devices). We also confirmed that this flip chip bonding was very stable after 1000 heat cycles. This new flip-chip-bonding technique should be very useful for making future high-speed optical transmission systems and the parallel optical interconnections required for electrical and photonic devices that will be used to create stable high-speed and high-density interconnections.

Photonic band gaps with layer-by-layer double-etched structures

Periodic layer-by-layer dielectric structures with full three-dimensional photonic band gaps have been designed and fabricated. In contrast to previous layer-by-layer structures the rods in each successive layer are at an angle of 70.5° to each other, achieved by etching both sides of a silicon wafer. Photonic band-structure calculations are utilized to optimize the photonic band gap by varying the structural geometry. The structure has been fabricated by double etching Si wafers producing millimeter wave photonic band gaps between 300 and 500 GHz, in excellent agreement with band calculations. Overetching this structure produces a multiply connected geometry and increases both the size and frequency of the photonic band gap, in very good agreement with experimental measurements. This new robust double-etched structure doubles the frequency possible from a single Si wafer, and can be scaled to produced band gaps at higher frequencies.

Surface conductivity for Au or Ag on Si(111).

The surface electrical conductivity was separated from the bulk one by simultaneous conductivity measurements of two different surface structures formed on a single Si-wafer surface in ultrahigh vacuum. We have found that the surface conductivities for the Si(111)-\ensuremath{\surd}3\ifmmode\times\else\texttimes\fi{}\ensuremath{\surd}3-Ag and -5\ifmmode\times\else\texttimes\fi{}2-Au superstructures are inherently higher than that of the Si(111)-7\ifmmode\times\else\texttimes\fi{}7 clean surface by (11.5\ifmmode\pm\else\textpm\fi{}0.5)\ifmmode\times\else\texttimes\fi{}${10}^{\mathrm{\ensuremath{-}}5}$ A/V and (5\ifmmode\pm\else\textpm\fi{}1)\ifmmode\times\else\texttimes\fi{}${10}^{\mathrm{\ensuremath{-}}5}$ A/V, respectively. These excess conductivities are estimated to originate mainly from the surface space-charge layer, although the surface-state-band conduction is considered to partly contribute, especially on the \ensuremath{\surd}3\ifmmode\times\else\texttimes\fi{}\ensuremath{\surd}3-Ag surface. \textcopyright{} 1996 The American Physical Society.

Heterogeneous silicon crystal growth on a single crystal silicon wafer by a molten silicon spraying deposition method

Using a new process, a polycrystalline silicon layer has been grown directly from molten Si at a rate 100 times faster than using a conventional CVD process. This has been achieved on a single Si wafer on which V grooves had been etched on an oxide layer. Thicknesses of 100–1000 μm and a grain sizes of 10–100 μm were controllably obtained. After the growth of the polycrystalline layer, dislocation densities of 2.0×10 5 cm -2 were found in the single crystal substrate and 2.8×10 5 cm -2 in the polycrystalline layer. A substrate with these dislocation densities is sufficient to use for dielectrically isolated (DI) substrates.

Silicon photodiode for optical channel waveguides

An etched mesa silicon photodiode suitable for detecting light propagating in optical channel waveguides has been fabricated. The diode width of 7 μm was slightly less than that of the channel waveguide, thus minimizing junction capacitance and the effect of detection noise caused by unguided substrate light. The fabrication technique can be applied to produce on a single Si wafer multiple photodiodes electrically isolated from each other. Optical energy was coupled from (out-diffused)LiNbO3 channel waveguides into the photodiodes by means of evanescent field coupling.