Single Processor Research Articles

A LAMMPS implementation of granular mechanics: Inclusion of adhesive and microscopic friction forces

A model for μm-sized grain–grain interaction is presented, which exhibits the essential features necessary to describe collision, agglomeration and fragmentation processes. The model has been efficiently implemented in the LAMMPS code. In addition to existing models, adhesive forces and — gliding, rolling, and torsional — friction processes are implemented. The code scales linearly with grain number up to ∼106 on a single processor and inherits the excellent parallelization features of the LAMMPS code on multi-processor machines. We validate the code by determining the velocity of sound of granular agglomerates.

Modeling and Control of a Flux-Modulated Compound-Structure Permanent-Magnet Synchronous Machine for Hybrid Electric Vehicles

The compound-structure permanent-magnet synchronous machine (CS-PMSM), comprising a double rotor machine (DRM) and a permanent-magnet (PM) motor, is a promising electronic-continuously variable transmission (e-CVT) concept for hybrid electric vehicles (HEVs). By CS-PMSM, independent speed and torque control of the vehicle engine is realized without a planetary gear unit. However, the slip rings and brushes of the conventional CS-PMSM are considered a major drawback for vehicle application. In this paper, a brushless flux-modulated CS-PMSM is investigated. The operating principle and basic working modes of the CS-PMSM are discussed. Mathematical models of the CS-PMSM system are given, and joint control of the two integrated machines is proposed. As one rotor of the DRM is mechanically connected with the rotor of the PM motor, special rotor position detection and torque allocation methods are required. Simulation is carried out by Matlab/Simulink, and the feasibility of the control system is proven. Considering the complexity of the controller, a single digital signal processor (DSP) is used to perform the interconnected control of dual machines instead of two separate ones, and a typical hardware implementation is proposed.

Cardiovascular System Modeling

Cardiovascular System Modeling

Simulations of Complex and Microscopic Models of Cardiac Electrophysiology Powered by Multi-GPU Platforms

Key aspects of cardiac electrophysiology, such as slow conduction, conduction block, and saltatory effects have been the research topic of many studies since they are strongly related to cardiac arrhythmia, reentry, fibrillation, or defibrillation. However, to reproduce these phenomena the numerical models need to use subcellular discretization for the solution of the PDEs and nonuniform, heterogeneous tissue electric conductivity. Due to the high computational costs of simulations that reproduce the fine microstructure of cardiac tissue, previous studies have considered tissue experiments of small or moderate sizes and used simple cardiac cell models. In this paper, we develop a cardiac electrophysiology model that captures the microstructure of cardiac tissue by using a very fine spatial discretization (8 μm) and uses a very modern and complex cell model based on Markov chains for the characterization of ion channel's structure and dynamics. To cope with the computational challenges, the model was parallelized using a hybrid approach: cluster computing and GPGPUs (general-purpose computing on graphics processing units). Our parallel implementation of this model using a multi-GPU platform was able to reduce the execution times of the simulations from more than 6 days (on a single processor) to 21 minutes (on a small 8-node cluster equipped with 16 GPUs, i.e., 2 GPUs per node).

Scalable and modular pervasive logic/firmware design

With the advances in semiconductor technology, more and more units such as cores, caches, memory controller, and input/output (I/O) can be integrated on a single processor. The latest generation of the IBM System z® processor family exploits these technology capabilities and integrates four cores, along with several cache, memory, and I/O units on a single die. More parallel units not only promise increased throughput but also add significant complexity to all chip-wide functions such as on-chip communication among the units. Many of the System z reliability, availability, and serviceability features are based on chip-wide functions, which are referred to as pervasive functions. Among others, the pervasive functions include chip initialization, test, control of clocks, monitoring of status information, and error reporting during system operation, as well as system reconfiguration while the system is running. As the complexity of many pervasive functions dramatically grows with the increasing number of integrated units, a new modular and scalable architecture for pervasive functions has been developed for the IBM zEnterprise® 196 processor (central processor (CP) chip) and system controller (SC chip) to cope with these challenges. This paper outlines the architecture for the CP and SC chips as they pertain to pervasive design. We discuss the architecture considerations taken when the new pervasive architecture was devised and elaborate on the implementation. Furthermore, we show how the novel pervasive architecture is used for very-large-scale integration testing, how it supports power management features, and how it facilitates a modular firmware design.

A Heterogeneous Multi-core Architecture with a Hardware Kernel for Control Systems

Rapid industrialisation has resulted in a demand for improved embedded control systems with features such as predictability, high processing performance and low power consumption. Software kernel implementation on a single processor is becoming more difficult to satisfy those constraints. This paper presents a multi-core architecture incorporating a hardware kernel on FPGAs, intended for high performance applications in control engineering domain. First, the hardware kernel is investigated on the basis of a component-based real-time kernel HARTEX (Hard Real-Time Executive for Control Systems). Second, a heterogeneous multi-core architecture is investigated, focusing on its performance in relation to hard real-time constraints and predictable behavior. Third, the hardware implementation of HARTEX is designated to support the heterogeneous multi-core architecture. This hardware kernel has several advantages over a counterpart kernel implemented in software: higher-speed processing capability, parallel computation, and separation between the kernel itself and the applications being run. A microbenchmark has been used to compare the hardware kernel with the software kernel, and compare the kernel on the multi-core platform with the kernel on the single-core platform.

Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

One of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify the conventional CORDIC algorithm to reduce its latency and area. The proposed CORDIC algorithm is completely scale-free for the range of convergence that spans the entire coordinate space. Secondly, we realize the window functions using a single CORDIC processor as against two serially connected CORDIC processors in existing technique, thus optimizing it for area and latency. The linear CORDIC processor is replaced by a shift-add network which drastically reduces the number of pipelining stages required in the existing design. The proposed design on an average requires approximately 64% less pipeline stages and saves up to 44.2% area. Currently, the processor is designed to implement Blackman windowing architecture, which with slight modifications can be extended to other widow functions as well. The details of the proposed architecture are discussed in the paper.

Low Cost Parallel Processing System for Image Processing Applications

The rapid grows in the image processing systems complexity, and the complicated nature of its new technologies system design, had created the need for a high speed embedded processing units at low costs. This paper proposes a new implementation method of low cost parallel processing system for image processing applications. The proposed method is implied two stages. The first stage focused in the implementation of the hardware of parallel processors, where two ARM technology processors are used for its considerably low cost, and as standard technology for processors. This stage also concerned about the overall system firmware requirements and system integrations. The second part of the work is to design the tasks parallelism between processors, and the overall system display. The complete system is tested for a real image processing data, and compared with a single processor system. The obtained results show that, the new system is significantly improved the processing in term of speed.

Multiple System Configurations in a 32-bit Extreme Environment

Full computational systems are needed at extreme environments (to 300°C) to increase functionality and reduce cost in the ever advancing oil/gas, geothermal, aeronautic, and automotive industries. Commercially available electronic components are not available to build a reliable system. A single microcontroller device can be used in systems of varying complexity, from small, mid, large, and multiprocessor scale. The 32-bit microcontroller will use a low power silicon-on-insulator CMOS process to increase long term reliability. Communication ports are provided to allow for simple systems with a single processor to complex multiprocessor systems with multiple controlled devices and external memory. As no adequate non-volatile solution is available for extreme conditions, multiple boot options are available to load instructions from external sources. Fault tolerance should be provided by system error detection. Battery backup must be provided for program and data retention. The resulting microcontroller will allow a wide variety of extreme environment systems, from simple to complex.

Toward a full-scale computational model of the rat dentate gyrus

Recent advances in parallel computing, including the creation of the parallel version of the NEURON simulation environment, have allowed for a previously unattainable level of complexity and detail in neural network models. Previously, we published a functional NEURON model of the rat dentate gyrus with over 50,000 biophysically realistic, multicompartmental neurons, but network simulations could only utilize a single processor. By converting the model to take advantage of parallel NEURON, we are now able to utilize greater computational resources and are able to simulate the full-scale dentate gyrus, containing over a million neurons. This has eliminated the previous necessity for scaling adjustments and allowed for a more direct comparison to experimental techniques and results. The translation to parallel computing has provided a superlinear speedup of computation time and dramatically increased the overall computer memory available to the model. The incorporation of additional computational resources has allowed for more detail and elements to be included in the model, bringing the model closer to a more complete and accurate representation of the biological dentate gyrus. As an example of a major step toward an increasingly accurate representation of the biological dentate gyrus, we discuss the incorporation of realistic granule cell dendrites into the model. Our previous model contained simplified, two-dimensional dendritic morphologies that were identical for neurons of the same class. Using the software tools L-Neuron and L-Measure, we are able to introduce cell-to-cell variability by generating detailed, three-dimensional granule cell morphologies that are based on biological reconstructions. Through these and other improvements, we aim to construct a more complete full-scale model of the rat dentate gyrus, to provide a better tool to delineate the functional role of cell types within the dentate gyrus and their pathological changes observed in epilepsy.

GPU implementations of the bond fluctuation model

We present two parallel implementations of the bond fluctuation model on graphics processors that outperform by a factor of up to 50 times an equivalent implementation on single CPU processor. The first algorithm is a parallelized version of an accelerated MC method published earlier in [S. Nedelcu, J.-U. Sommer, Single chain dynamics in polymer networks: a Monte Carlo study, J. Chem. Phys. 130 (2009) 204902]. In this first algorithm we use the parallel domain decomposition technique to avoid monomer collisions. In contrast, in the second algorithm we associate each monomer with a parallel process, where all monomers in the system are attempted to move simultaneously. In both cases, only monomer moves that result in allowed bonds and preserve lattice occupancy are accepted. To validate the correctness of the GPU algorithms we simulated monodisperse polymer melts at monomer number density 0.5 and compared static and dynamical properties with standard CPU implementations. We found good agreement between the CPU and the GPU results, which demonstrates the equivalence of the serial and parallel implementations. The influence of higher monomer number density is discussed.

ESpritz: accurate and fast prediction of protein disorder

Intrinsically disordered regions are key for the function of numerous proteins, and the scant available experimental annotations suggest the existence of different disorder flavors. While efficient predictions are required to annotate entire genomes, most existing methods require sequence profiles for disorder prediction, making them cumbersome for high-throughput applications. In this work, we present an ensemble of protein disorder predictors called ESpritz. These are based on bidirectional recursive neural networks and trained on three different flavors of disorder, including a novel NMR flexibility predictor. ESpritz can produce fast and accurate sequence-only predictions, annotating entire genomes in the order of hours on a single processor core. Alternatively, a slower but slightly more accurate ESpritz variant using sequence profiles can be used for applications requiring maximum performance. Two levels of prediction confidence allow either to maximize reasonable disorder detection or to limit expected false positives to 5%. ESpritz performs consistently well on the recent CASP9 data, reaching a S(w) measure of 54.82 and area under the receiver operator curve of 0.856. The fast predictor is four orders of magnitude faster and remains better than most publicly available CASP9 methods, making it ideal for genomic scale predictions. ESpritz predicts three flavors of disorder at two distinct false positive rates, either with a fast or slower and slightly more accurate approach. Given its state-of-the-art performance, it can be especially useful for high-throughput applications. Both a web server for high-throughput analysis and a Linux executable version of ESpritz are available from: http://protein.bio.unipd.it/espritz/.

Simulation-based comparison of scheduling techniques in multiprogramming operating systems on single and multi-core processors

The operating systems course is one of the essential courses in the computer science curriculum, and CPU scheduling is a crucial component of this course. Multi-core processors have become the norm...

Design of Wireless Acceleration Sensor Nodes Used in Mechanical Equipment Status Monitoring

Wireless Sensor Network is a new integrated technology, which combines sensor technology, wireless communication technology, Micro-Electro-Mechanical Systems technology and Digital electronic technology. Now, it has been widely used in military, industrial control, environmental monitoring, transportation, and medical. Along with the research evolution on Wireless Sensor Network, its application fields are gradually expanding. It is penetrating deep into each aspect of the human’s production and life, and will be a new revolutionary technology. In this paper, a wireless acceleration node based on wireless single chip processor CC2430, an ARM7TDMI-S core based microcontroller called LPC2478 microprocessor and three-axis acceleration sensor ADXL330 is designed to monitor the mechanical system operation conditions and fault diagnosis with high efficiency. The performance and characteristics of CC2430, ADXL330 and LPC2478 are introduced compactly. The designations of hardware as well as software of wireless network node are introduced in details. The nodes perform steadily and efficiently in practical test, and it can be easily applied to other monitoring areas.

Parallel anisotropic mesh adaptivity with dynamic load balancing for cardiac electrophysiology

Simulations in cardiac electrophysiology generally use very fine meshes and small time steps to resolve highly localized wavefronts. This expense motivates the use of mesh adaptivity, which has been demonstrated to reduce the overall computational load. However, even with mesh adaptivity performing such simulations on a single processor is infeasible. Therefore, the adaptivity algorithm must be parallelised. Rather than modifying the sequential adaptive algorithm, the parallel mesh adaptivity method introduced in this paper focuses on dynamic load balancing in response to the local refinement and coarsening of the mesh. In essence, the mesh partition boundary is perturbed away from mesh regions of high relative error, while also balancing the computational load across processes. The parallel scaling of the method when applied to physiologically realistic heart meshes is shown to be good as long as there are enough mesh nodes to distribute over the available parallel processes. It is shown that the new method is dominated by the cost of the sequential adaptive mesh procedure and that the parallel overhead of inter-process data migration represents only a small fraction of the overall cost.

A parallel programming model for ada

Over the last three decades, computer architects have been able to achieve an increase in performance for single processors by, e.g., increasing clock speed, introducing cache memories and using instruction level parallelism. However, because of power consumption and heat dissipation constraints, this trend is going to cease. In recent times, hardware engineers have instead moved to new chip architectures with multiple processor cores on a single chip. With multi-core processors, applications can complete more total work than with one core alone. To take advantage of multi-core processors, parallel programming models are proposed as promising solutions for more effectively using multi-core processors. This paper discusses some of the existent models and frameworks for parallel programming, leading to outline a draft parallel programming model for Ada.

Testing large-scale cloud management

Testing for correctness and reliability is a major challenge in the development and deployment of cloud computing platforms. Testing a cloud composed of hundreds to thousands of servers is often cost-prohibitive because of the extensive amount of hardware required. Simulation and emulation, i.e., traditional alternatives to hardware, are too abstract or too slow for testing production code in environments with many servers. We propose a testing approach that combines simulation and emulation in a cloud simulator that runs on a single processor yet enables testing of cloud management software as if the software were managing hundreds of servers and thousands of virtual machine instances. This approach alleviates a significant obstacle on the path to high-quality cloud computing systems.

Neighbourhood Properties in Some Single Processor Scheduling Problem with Variable Efficiency and Additional Resources

In the paper, we consider a problem of scheduling a set of tasks on a single processor. Each task must be preprocessed before it can be started on a processor. The efficiency of preprocessing is variable, i.e., the rate of the task preprocessing depends on the amount of continuously divisible resource allotted to this task. This dependency is given by concave, continuous, non-negative and strictly increasing function of the resource amount. The total consumption of resource at each moment is upper bounded. The objective is to minimize the maximum task completion time. The considered problem is NP-hard. Such a problem appears, e.g., in steel mill systems, where ingots (before hot rolling on the blooming mill) have to achieve the required temperature in the preheating process in soaking pits. Some new properties of the problem are proved. These properties are used to construct the procedure for evaluation of the neighbourhood. The procedure is proposed to improve the efficiency of algorithms based on the neighbourhood concept, such as metaheuristics. The computational experiment is conducted to examine the efficiency of the proposed procedure. The described approach can be easily used in the other discrete-continuous scheduling problems.

Analysis Of Time Triggered Schedulers In Embedded System

In embedded software, scheduler is one of the essential component. It is essential to schedule the task in a suitable way to achieve the system optimization. Time triggered scheduling approaches render a reliable performance for real time systems. This paper sketches on time triggered schedulers which tends to results in highly predictable system behavior. Despite many scheduling approaches, time triggered cooperative and time triggered hybrid schedulers have more attention in resource constrained embedded system which works on single processor. Our target of this work is to analyze these time triggered schedulers’ performances. We evaluated and studied the performance of those time triggered schedulers with various parameters. The results have been incurred by implementation of schedulers in embedded c programming language with simulation tool.

Conditional-Fault Diagnosability of Multiprocessor Systems with an Efficient Local Diagnosis Algorithm under the PMC Model

Diagnosis is an essential subject for the reliability of multiprocessor systems. Under the PMC diagnosis model, Dahbura and Masson proposed a polynomial-time algorithm with time complexity O(N2.5) to identify all the faulty processors in a system with N processors. In this paper, we present a novel method to diagnose a conditionally faulty system by applying the concept behind the local diagnosis, introduced by Somani and Agarwal, and formalized by Hsu and Tan. The goal of local diagnosis is to identify the fault status of any single processor correctly. Under the PMC diagnosis model, we give a sufficient condition to estimate the local diagnosability of a given processor. Furthermore, we propose a helpful structure, called the augmenting star, to efficiently determine the fault status of each processor. For an N-processor system in which every processor has an O(log N) degree, the time complexity of our algorithm to diagnose any given processor is O((log N)2), provided that each processor can construct an augmenting star structure of full order in time O((log N)2) and the time for a processor to test another one is constant. Therefore, the time totals to O(N(log N)2) for diagnosing the whole system.